公开(公告)号：US11961842B2

公开(公告)日：2024-04-16

申请号：US18224666

申请日：2023-07-21

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake

IPC分类号： H01L27/12 ,  H01L27/088 ,  H01L29/04 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/49

CPC分类号： H01L27/1225 ,  H01L27/0883 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/045 ,  H01L29/24 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L21/02603 ,  H01L29/04 ,  H01L29/4908 ,  H01L2924/13069

摘要： An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

公开(公告)号：US09972646B2

公开(公告)日：2018-05-15

申请号：US15224065

申请日：2016-07-29

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Masayuki Sakakura ,  Shunpei Yamazaki

IPC分类号： H01L27/146 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36 ,  H01L27/02 ,  H01L27/32 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1333

CPC分类号： H01L27/1244 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/123 ,  G09G3/2007 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0235 ,  H01L27/0255 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1274 ,  H01L27/3223 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78663 ,  H01L29/78675 ,  H01L2227/323 ,  H01L2924/13069

摘要： An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

公开(公告)号：US09681545B2

公开(公告)日：2017-06-13

申请号：US15187371

申请日：2016-06-20

申请人： INNOLUX CORPORATION

发明人： Chia-Cheng Liu ,  Chia-Hsiung Chang ,  An-Chang Wang ,  Chao-Hsiang Wang ,  Yang-Chen Chen

IPC分类号： H05K1/11 ,  H05K1/09 ,  H01L23/00 ,  H05K3/32 ,  G02F1/1345 ,  H01L23/492

CPC分类号： H05K1/111 ,  G02F1/1345 ,  G02F1/13458 ,  H01L23/4922 ,  H01L24/06 ,  H01L24/07 ,  H01L24/09 ,  H01L24/26 ,  H01L24/31 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2225/1041 ,  H01L2924/13069 ,  H01L2924/365 ,  H05K1/092 ,  H05K1/117 ,  H05K3/323 ,  H05K2201/10136

摘要： A substrate structure includes a first substrate, a plurality of first bonding pads, a second substrate and a connecting layer. The first substrate has an element configuration area and a peripheral area. The peripheral area is located around the element configuration area. The first bonding pads are configured spacing at the peripheral area, and a gap is provided between two adjacent first bonding pads. The first bonding pads are located between the first substrate and the second substrate. The connecting layer is located between the first bonding pads and the second substrate. The part of the connecting layer close to the element configuration area is configured with a plurality of first arc edges.

公开(公告)号：US20160336353A1

公开(公告)日：2016-11-17

申请号：US15224065

申请日：2016-07-29

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Masayuki SAKAKURA ,  Shunpei YAMAZAKI

IPC分类号： H01L27/12 ,  H01L29/786 ,  G09G3/36 ,  G02F1/1362 ,  G09G3/20 ,  H01L27/02 ,  G02F1/1368

CPC分类号： H01L27/1244 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/123 ,  G09G3/2007 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0235 ,  H01L27/0255 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1274 ,  H01L27/3223 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78663 ,  H01L29/78675 ,  H01L2227/323 ,  H01L2924/13069

摘要： An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even when the insulating film provided between adjacent pixels is formed by a coating method, thin portions are problematically partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wiring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

摘要翻译： 设置在相邻像素之间的绝缘膜被称为堤，隔板，阻挡层，路堤等，并且设置在用于薄膜晶体管或电源线的源极布线或漏极布线的上方。 特别地，在这些布线的交叉部分设置在不同的层中，在其中形成比其他部分更大的台阶。 即使通过涂布法形成设置在相邻像素之间的绝缘膜，也由于该步骤而有限度地形成薄壁部分，并且耐压降低。 在本发明中，在大台阶部分附近设置虚拟材料，特别是布置在配线的交叉部分周围，以减轻形成在其上的不均匀。 上部布线和下部布线以不对准的方式布置，以便不使端部对准。

公开(公告)号：US09384439B2

公开(公告)日：2016-07-05

申请号：US11596806

申请日：2005-06-10

申请人： Shunpei Yamazaki ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Kiyoshi Kato

IPC分类号： G06K19/06 ,  G06K19/077 ,  H01L27/12

CPC分类号： H01L27/1218 ,  G02F1/13338 ,  G02F1/1368 ,  G06K7/10217 ,  G06K19/07749 ,  H01L23/66 ,  H01L24/32 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1266 ,  H01L29/78678 ,  H01L29/78696 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2924/13069 ,  H01L2924/141 ,  H01L2924/1432 ,  H01L2924/1579

摘要： It is an object of the present invention to provide a semiconductor device in which a sophisticated integrated circuit using a polycrystalline semiconductor is formed over a substrate which is weak with heat such as a plastic substrate or a plastic film substrate and a semiconductor device which transmits/receives power or a signal without wires, and a communication system thereof. One feature of the invention is that a semiconductor device, specifically, a processor, in which a sophisticated integrated circuit is fixed to a plastic substrate which is weak with heat by a stripping method such as a stress peel of process method to transmit/receive power or a signal without wires, for example, with an antenna or a light receiving element.

摘要翻译： 本发明的目的是提供一种半导体器件，其中使用多晶半导体的复杂集成电路形成在诸如塑料基板或塑料薄膜基板的热弱的基板上，并且半导体器件透射/ 接收电力或没有电线的信号，以及其通信系统。 本发明的一个特征在于，一种半导体装置，特别是一种处理器，其中一个复杂的集成电路固定在一个塑料基板上，该塑料基板通过诸如剥离方法的热而被加热，该剥离方法用于传递/接收电力 或没有电线的信号，例如具有天线或光接收元件。

公开(公告)号：US20120248448A1

公开(公告)日：2012-10-04

申请号：US13444565

申请日：2012-04-11

申请人： Masayuki Sakakura ,  Shunpei Yamazaki

发明人： Masayuki Sakakura ,  Shunpei Yamazaki

IPC分类号： H01L29/786

CPC分类号： H01L27/1244 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/123 ,  G09G3/2007 ,  G09G3/36 ,  G09G2300/0426 ,  G09G2310/0235 ,  H01L27/0255 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1274 ,  H01L27/3223 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78663 ,  H01L29/78675 ,  H01L2227/323 ,  H01L2924/13069

摘要： An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even in a case that the insulating film provided between adjacent pixels is formed by a coating method, there is a problem that thin portions are partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

摘要翻译： 设置在相邻像素之间的绝缘膜被称为堤，隔板，阻挡层，路堤等，并且设置在用于薄膜晶体管或电源线的源极布线或漏极布线的上方。 特别地，在这些布线的交叉部分设置在不同的层中，在其中形成比其他部分更大的台阶。 即使在通过涂布法形成相邻像素之间的绝缘膜的情况下，存在由于该步骤而部分地形成薄壁部分并且耐受压力降低的问题。 在本发明中，在大台阶部分附近设置虚拟材料，特别是布置在配线的交叉部分周围，以减轻形成在其上的不均匀。 上部绞线和下部布线以不对准的方式布置，以便不使端部对齐。

公开(公告)号：US20180337196A1

公开(公告)日：2018-11-22

申请号：US15973854

申请日：2018-05-08

申请人： GIO Optoelectronics Corp.

发明人： Wu-Chang YANG

IPC分类号： H01L27/12 ,  H01L23/00 ,  H01L25/16

CPC分类号： H01L27/124 ,  H01L21/32133 ,  H01L24/16 ,  H01L24/81 ,  H01L25/167 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/127 ,  H01L27/307 ,  H01L27/3276 ,  H01L33/62 ,  H01L51/0097 ,  H01L2224/16145 ,  H01L2224/81005 ,  H01L2227/326 ,  H01L2251/5338 ,  H01L2251/558 ,  H01L2924/12041 ,  H01L2924/13069 ,  H01L2933/0066

摘要： An electronic device and a manufacturing method thereof are disclosed. The manufacturing method of an electronic device includes following steps: forming a flexible substrate on a rigid carrier plate; forming at least a thin-film device on the flexible substrate; forming a conductive line on the flexible substrate, wherein the conductive line is electrically connected with the thin-film device; forming at least an electrical connection pad on the flexible substrate, wherein the electrical connection pad is electrically connected with the conductive line, and the thickness of the electrical connection pad is between 2 and 20 microns; disposing at least a surface-mount device (SMD) on the flexible substrate, wherein the SMD is electrically connected with the thin-film device through the electrical connection pad and the conductive line; and removing the rigid carrier plate.

公开(公告)号：US10079264B2

公开(公告)日：2018-09-18

申请号：US15135217

申请日：2016-04-21

申请人： Hong Kong Beida Jade Bird Display Limited

发明人： Lei Zhang ,  Fang Ou ,  Qiming Li

IPC分类号： H01L23/29 ,  H01L25/16 ,  H01L27/15 ,  H01L23/00 ,  H01L27/12

CPC分类号： H01L27/156 ,  H01L23/29 ,  H01L24/73 ,  H01L25/16 ,  H01L25/167 ,  H01L27/1255 ,  H01L2224/73253 ,  H01L2924/12041 ,  H01L2924/13069 ,  H01L2924/1426 ,  H01L2924/1431

摘要： Various embodiments include a semiconductor device with thin-film transistor (TFT) circuitry monolithically integrated with other non-TFT functional devices. One example is an integrated LED display panel, in which an array of LEDs is integrated with corresponding TFT driver circuitry. The TFT driver circuitry typically is an array of pixel drivers that drive the LEDs.

公开(公告)号：US20180019234A1

公开(公告)日：2018-01-18

申请号：US15644047

申请日：2017-07-07

申请人： InnoLux Corporation

发明人： Shun-Yuan HU

IPC分类号： H01L25/16 ,  H01L33/62 ,  H01L23/00 ,  H01L25/075 ,  H01L27/12

CPC分类号： H01L25/167 ,  H01L24/03 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0753 ,  H01L27/1244 ,  H01L33/62 ,  H01L2224/16148 ,  H01L2224/1703 ,  H01L2224/32148 ,  H01L2224/73204 ,  H01L2224/9211 ,  H01L2924/12041 ,  H01L2924/13069 ,  H01L2933/0066

摘要： A display device is provided. The display device includes a first conductive pad disposed on a substrate, wherein the first conductive pad has a contact area that is adjacent to the substrate. The display device also includes a first bonding material disposed on the first conductive pad, wherein the first bonding material has a sectional area that is parallel to a surface of the substrate. The display device further includes a second conductive pad disposed on the first bonding material, and a first illumination structure disposed on the second conductive pad, wherein the sectional area of the first bonding material is smaller than the contact area of the first conductive pad.

公开(公告)号：US20170256583A1

公开(公告)日：2017-09-07

申请号：US15440329

申请日：2017-02-23

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Sukho CHOI ,  Euttum KIM ,  Joonsam KIM

IPC分类号： H01L27/18 ,  H05K1/18 ,  H01L23/00 ,  H05K1/09

CPC分类号： H01L24/73 ,  G02F1/13452 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/13069 ,  H01L2924/1426 ,  H01L2924/3511 ,  H05K3/323 ,  H05K2201/0266 ,  H05K2201/10128

摘要： A display apparatus includes a display panel, a driving integrated circuit (IC), and an anisotropic conductive film. The display panel includes a non-display area adjacent to a display area and an upper substrate and a lower substrate. The driving IC overlaps the non-display area. The anisotropic conductive film attaches the driving IC to the lower substrate and includes conductive balls with diameters that gradually increase toward the display area.