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206 条记录 (耗时 0.051 秒)

    Integrated circuit having embedded differential clock tree
    92.
    发明授权
    Integrated circuit having embedded differential clock tree 有权
    集成电路具有嵌入式差分时钟树

    公开(公告)号：US07759973B1

    公开(公告)日：2010-07-20

    申请号：US12174502

    申请日：2008-07-16

    申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    IPC分类号： H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

    Gating logic circuits in a self-timed integrated circuit
    93.
    发明授权
    Gating logic circuits in a self-timed integrated circuit 有权
    门自动定时逻辑电路集成电路

    公开(公告)号：US07746111B1

    公开(公告)日：2010-06-29

    申请号：US12417033

    申请日：2009-04-02

    申请人： Brian C. Gaide ,  Steven P. Young

    发明人： Brian C. Gaide ,  Steven P. Young

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/17736

    摘要： Circuits for implementing gating logic in a self-timed integrated circuit. An integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. Each output circuit has a data input coupled to an output of the logic circuit, a gating input, and a data output coupled to an output of the logic block. The output circuit is coupled to place a value on the data input onto the data output when the gating input has a first value and the output circuit receives tokens indicating valid new data on both the data input and the gating input of the output circuit. The output circuit is coupled to leave the data output unchanged when the gating input has a second value and the output circuit receives a token indicating valid new data on both the data and gating inputs of the output circuit.

    摘要翻译： 用于在自定时集成电路中实现门控逻辑的电路。 集成电路包括多个互连的逻辑块，每个逻辑块包括逻辑电路和输出电路。 每个输出电路具有耦合到逻辑电路的输出，门控输入和耦合到逻辑块的输出的数据输出的数据输入。 当门控输入具有第一值时，输出电路被耦合以将数据输入到数据输出上，并且输出电路在输出电路的数据输入和门控输入端接收指示有效新数据的令牌。 当门控输入具有第二值时，输出电路被耦合以保持数据输出不变，并且输出电路在输出电路的数据和选通输入端接收到指示有效新数据的令牌。

    Circuits for fanning out data in a programmable self-timed integrated circuit
    94.
    发明授权
    Circuits for fanning out data in a programmable self-timed integrated circuit 有权
    用于在可编程自定时集成电路中扇出数据的电路

    公开(公告)号：US07746110B1

    公开(公告)日：2010-06-29

    申请号：US12417023

    申请日：2009-04-02

    申请人： Brian C. Gaide ,  Steven P. Young

    发明人： Brian C. Gaide ,  Steven P. Young

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/17736

    摘要： Circuits for fanning out data in a self-timed integrated circuit. An exemplary integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. The output circuit has a first data input coupled to a first output of the logic circuit, a second data input coupled to a second output of the logic circuit, and a data output coupled to a first output of the logic block. The data output reflects a value on the first data input. The output circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token only when the first data input is accompanied by a first token indicating valid new data on the first data input. The output circuit is further programmably coupled to consume, when the output token is provided, both the first token and a second token accompanying the second data input.

    摘要翻译： 用于在自定时集成电路中扇出数据的电路。 示例性集成电路包括多个互连的逻辑块，每个逻辑块包括逻辑电路和输出电路。 输出电路具有耦合到逻辑电路的第一输出的第一数据输入，耦合到逻辑电路的第二输出的第二数据输入和耦合到逻辑块的第一输出的数据输出。 数据输出反映第一个数据输入的值。 输出电路可编程地以多种操作模式之一耦合，以仅在第一数据输入伴随有指示有效的新数据在第一数据输入上的第一标记时提供输出令牌。 当提供输出令牌时，输出电路进一步可编程地耦合以消耗第一令牌和伴随第二数据输入的第二令牌。

    Cascading input structure for logic blocks in integrated circuits
    95.
    发明授权
    Cascading input structure for logic blocks in integrated circuits 有权
    集成电路中逻辑块的级联输入结构

    公开(公告)号：US07746101B1

    公开(公告)日：2010-06-29

    申请号：US12417015

    申请日：2009-04-02

    申请人： Steven P. Young

    发明人： Steven P. Young

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17728 ,  H03K19/17736

    摘要： A cascading input structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes a plurality of substantially similar logic blocks arrayed to form a column of the logic blocks, and a self-timed vertical cascade chain. Each of the logic blocks has self-timed first and second inputs. The vertical cascade chain has a plurality of self-timed outputs, each of the self-timed outputs being coupled to a first self-timed input of a corresponding logic block in the column. In some embodiments, each logic block includes a multiply block having first and second self-timed inputs, where each output of the vertical cascade chain is coupled to the first input of the multiply block in the corresponding logic block. In some embodiments having a multiply block in the logic block, the inputs and output may not be self-timed.

    摘要翻译： 集成电路中逻辑块的级联输入结构。 示例性的集成电路包括多个基本相似的逻辑块，其被排列以形成逻辑块的列，以及自定时垂直级联链。 每个逻辑块具有自定义的第一和第二输入。 垂直级联链具有多个自定时输出，每个自定时输出耦合到该列中对应的逻辑块的第一自定时输入。 在一些实施例中，每个逻辑块包括具有第一和第二自定时输入的乘法块，其中垂直级联链的每个输出耦合到相应逻辑块中的乘法块的第一输入。 在具有逻辑块中的乘法块的一些实施例中，输入和输出可以不是自定时的。

    Integrated circuits with novel handshake logic
    96.
    发明授权
    Integrated circuits with novel handshake logic 有权
    具有新颖握手逻辑的集成电路

    公开(公告)号：US07605604B1

    公开(公告)日：2009-10-20

    申请号：US12174945

    申请日：2008-07-17

    申请人： Steven P. Young

    发明人： Steven P. Young

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/17736 ,  H03K19/1776

    摘要： Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a first input coupled to a control output of the C-element, and a second input. The storage element includes a data multiplexer and a latch. The data multiplexer has M data inputs coupled to data inputs of the storage element, a select input coupled to the output of the logic gate, and a data output, M being an integer greater than one. The latch has a data input coupled to the data output of the first data multiplexer and an output coupled to an output of the storage element. The logic gate can be a logical AND gate with the second input coupled to a memory cell.

    摘要翻译： 提供具有新颖握手逻辑的集成电路（IC）。 IC包括就绪复用器，确认解复用器，耦合到就绪复用器和确认解复用器的C元件，逻辑门和存储元件（例如，锁存器）。 逻辑门具有耦合到C元件的控制输出的第一输入和第二输入。 存储元件包括数据多路复用器和锁存器。 数据多路复用器具有耦合到存储元件的数据输入的M个数据输入，耦合到逻辑门的输出的选择输入以及M是大于1的整数的数据输出。 锁存器具有耦合到第一数据多路复用器的数据输出的数据输入和耦合到存储元件的输出的输出。 逻辑门可以是与第二输入耦合到存储器单元的逻辑与门。

    CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY
    97.
    发明申请
    CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY 失效
    通过分离设备来表征电路性能和对信号延迟的互连影响

    公开(公告)号：US20090121737A1

    公开(公告)日：2009-05-14

    申请号：US12355988

    申请日：2009-01-19

    申请人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    发明人： Xiao-Jie Yuan ,  Michael J. Hart ,  Zicheng G. Ling ,  Steven P. Young

    IPC分类号： G01R31/26 ,  G01R31/02 ,  H01L23/58

    CPC分类号： G01R31/2882 ,  G01R31/318511 ,  G01R31/318516 ,  G01R31/3187

    摘要： An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.

    摘要翻译： 集成电路（IC）包括多个嵌入式测试电路，其中都包括耦合到测试负载的环形振荡器。 测试负载在环形振荡器中是直接短路，或者是表示IC中互连层之一的互连负载。 为每个嵌入式测试电路定义一个模型方程，每个模型方程式将其相关嵌入式测试电路的输出延迟指定为线路前端（FEOL）和线路后端（BEOL）参数的函数。 然后，对于各种FEOL和BEOL参数求解模型方程，作为测试电路输出延迟的函数。 最后，将测量的输出延迟值替换为这些参数方程，以生成各种FEOL和BEOL参数的实际值，从而允许快速准确地识别任何关注的领域。

    Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit
    98.
    发明授权
    Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权
    用于在集成电路中提供频率合成和相位对准的方法和装置

    公开(公告)号：US07499513B1

    公开(公告)日：2009-03-03

    申请号：US11049329

    申请日：2005-02-02

    申请人： David E. Tetzlaff ,  F. Erich Goetting ,  Steven P. Young ,  Marwan M. Hassoun ,  Moises E. Robinson

    发明人： David E. Tetzlaff ,  F. Erich Goetting ,  Steven P. Young ,  Marwan M. Hassoun ,  Moises E. Robinson

    IPC分类号： H04L7/00 ,  H03L7/06

    CPC分类号： G06F1/10 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/183

    摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

    摘要翻译： 根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。 每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。 在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。

    Programmable logic device with cascading DSP slices
    100.
    发明授权
    Programmable logic device with cascading DSP slices 有权
    具有级联DSP片的可编程逻辑器件

    公开(公告)号：US07472155B2

    公开(公告)日：2008-12-30

    申请号：US11019783

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/38

    CPC分类号： H03K19/17736 ,  G06F15/7867 ,  H03K19/17732

    摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

    摘要翻译： 描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。 每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。 操作数端口接收处理的操作数，切片输出端口传送处理结果。 每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。