公开(公告)号：US20210391182A1

公开(公告)日：2021-12-16

申请号：US16901001

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/308 ,  G03F1/38

Abstract: A manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.

公开(公告)号：US20210375687A1

公开(公告)日：2021-12-02

申请号：US16887154

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

公开(公告)号：US11171061B2

公开(公告)日：2021-11-09

申请号：US16569820

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu Lee ,  Huicheng Chang ,  Che-Hao Chang ,  Ching-Hwanq Su ,  Weng Chang ,  Xiong-Fei Yu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

公开(公告)号：US11145751B2

公开(公告)日：2021-10-12

申请号：US15939389

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Su-Hao Liu ,  Chun-Hao Kung ,  Liang-Yin Chen ,  Huicheng Chang ,  Kei-Wei Chen ,  Hui-Chi Huang ,  Kao-Feng Liao ,  Chih-Hung Chen ,  Jie-Huang Huang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a dielectric layer, a contact plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The dielectric layer is positioned over the gate structure and the source/drain structure. The contact plug is positioned passing through the dielectric layer. The contact plug includes a first metal compound including one of group III elements, group IV elements, group V elements or a combination thereof.

公开(公告)号：US10950447B2

公开(公告)日：2021-03-16

申请号：US16907889

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20200321216A1

公开(公告)日：2020-10-08

申请号：US16907889

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa Luan ,  Yi-Fan Chen ,  Chun-Yen Peng ,  Cheng-Po Chau ,  Wen-Yu Ku ,  Huicheng Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/51 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20200083115A1

公开(公告)日：2020-03-12

申请号：US16686365

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kun-Yu Lee ,  Huicheng Chang ,  Che-Hao Chang ,  Ching-Hwanq Su ,  Weng Chang ,  Xiong-Fei Yu

IPC: H01L21/8238 ,  H01L27/092

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

公开(公告)号：US10510891B1

公开(公告)日：2019-12-17

申请号：US16504670

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L21/3115 ,  H01L21/02 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/165

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US20190378928A1

公开(公告)日：2019-12-12

申请号：US16504670

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ying-Lang Wang

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3215

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

公开(公告)号：US10460940B2

公开(公告)日：2019-10-29

申请号：US15920745

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Shun Chang ,  Chun-Feng Nieh ,  Huicheng Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/266 ,  H01L21/308 ,  H01L21/426

Abstract: Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.