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253 条记录 (耗时 0.044 秒)

    METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
    92.
    发明申请
    METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION 有权
    用于高密度等离子体化学蒸气沉积的方法和装置

    公开(公告)号：US20100029082A1

    公开(公告)日：2010-02-04

    申请号：US12185339

    申请日：2008-08-04

    申请人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

    发明人： Daewon Yang ,  Kangguo Cheng ,  Pavel Smetana ,  Richard S. Wise ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/311 ,  C23C16/00

    CPC分类号： C23C16/507 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45578 ,  C23C16/4586 ,  C23C16/56 ,  H01J37/20 ,  H01J37/321 ,  H01J2237/20207 ,  H01J2237/3323 ,  H01L21/31608 ,  H01L21/3185 ,  H01L27/10867

    摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

    摘要翻译： 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。

    Reversible electric fuse and antifuse structures for semiconductor devices
    95.
    发明授权
    Reversible electric fuse and antifuse structures for semiconductor devices 有权
    用于半导体器件的可逆电熔丝和反熔丝结构

    公开(公告)号：US07557424B2

    公开(公告)日：2009-07-07

    申请号：US11619264

    申请日：2007-01-03

    申请人： Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S Yang

    发明人： Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S Yang

    IPC分类号： H01L23/58

    CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements. In another embodiment, the method includes depositing a first and a second material layer on a semiconductor substrate, wherein the second material layer having a higher electrical conductivity than the first material layer; selectively etching the first and second material layer to create at least one constricted region to facilitate electromigration of the second material; wherein the electromigration creates a plurality of micro voids; and forming a plurality of electrical contacts on the second material layer.

    摘要翻译： 提供一种用于制造用于半导体器件的可逆熔丝和反熔丝结构的结构和方法。 在一个实施例中，该方法包括形成至少一条线，其具有用于暴露多个互连特征的一部分的通孔; 在通孔开口上共形沉积第一材料层; 在所述第一材料层上沉积第二材料层，其中所述沉积在所述通孔开口的顶部部分上突出所述第二材料层的一部分; 以及沉积绝缘材料的覆盖层，其中所述沉积形成多个熔丝元件，每个熔丝元件在所述绝缘材料和所述第二材料层之间具有气隙。 该方法还包括在连接熔丝元件的绝缘体材料中形成多个电镀层。 在另一个实施例中，该方法包括在半导体衬底上沉积第一和第二材料层，其中第二材料层具有比第一材料层更高的导电性; 选择性地蚀刻第一和第二材料层以产生至少一个收缩区域以促进第二材料的电迁移; 其中所述电迁移产生多个微空隙; 以及在所述第二材料层上形成多个电接触。

    Porous and dense hybrid interconnect structure and method of manufacture
    96.
    发明授权
    Porous and dense hybrid interconnect structure and method of manufacture 失效
    多孔密集混合互连结构及制造方法

    公开(公告)号：US07544608B2

    公开(公告)日：2009-06-09

    申请号：US11458464

    申请日：2006-07-19

    申请人： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

    发明人： Chih-Chao Yang ,  Keith Kwong Hon Wong ,  Haining Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L23/53295 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.

    摘要翻译： 一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。 该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。 半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

    DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE
    98.
    发明申请
    DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
    双层封装层互连结构

    公开(公告)号：US20080293257A1

    公开(公告)日：2008-11-27

    申请号：US12186923

    申请日：2008-08-06

    申请人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

    发明人： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

    摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

    摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。 高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。 每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

    Low resistance contact structure and fabrication thereof
    100.
    发明授权
    Low resistance contact structure and fabrication thereof 有权
    低电阻接触结构及其制造

    公开(公告)号：US07407875B2

    公开(公告)日：2008-08-05

    申请号：US11470349

    申请日：2006-09-06

    申请人： Keith Kwong Hon Wong ,  Patrick W. DeHaven ,  Sadanand V. Deshpande ,  Anita Madan

    发明人： Keith Kwong Hon Wong ,  Patrick W. DeHaven ,  Sadanand V. Deshpande ,  Anita Madan

    IPC分类号： H01L21/20 ,  H01L21/44

    CPC分类号： H01L21/76846 ,  H01L21/76856

    摘要： Embodiments of the present invention provide a method of fabricating a contact structure in a layer of dielectric material between a semiconductor device and a back-end-of-line interconnect. The method includes creating at least one contact opening in said layer of dielectric material; forming a first TiN film through a chemical-vapor deposition process, said first TiN film lining said contact opening; and forming a second TiN film through a physical vapor deposition process, said second TiN film lining said first TiN film. A contact structure fabricated according to embodiments of the invention is also provided.

    摘要翻译： 本发明的实施例提供一种在半导体器件和后端串联之间的电介质材料层中制造接触结构的方法。 该方法包括在所述介电材料层中形成至少一个接触开口; 通过化学气相沉积工艺形成第一TiN膜，所述第一TiN膜衬在所述接触开口上; 以及通过物理气相沉积工艺形成第二TiN膜，所述第二TiN膜衬在所述第一TiN膜上。 还提供了根据本发明的实施例制造的接触结构。