公开(公告)号：US20140118379A1

公开(公告)日：2014-05-01

申请号：US14012308

申请日：2013-08-28

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. HAKURA ,  Rouslan DIMITROV ,  Emmett M. KILGARIFF ,  Andrei KHODAKOVSKY

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/601 ,  G06T11/40 ,  G06T15/005 ,  G09G2360/121

Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.

Abstract translation: 本发明的一个实施例包括用于在图形系统中自动调整高速缓存块的尺寸的技术。 与图形系统相关联的设备驱动程序将与高速缓存平铺相关联的高速缓存平铺大小设置为第一大小。 检测从包括第一组渲染目标的第一渲染目标配置到包括第二组渲染目标的第二渲染目标配置的改变。 设备驱动程序基于第二渲染目标配置将高速缓存磁贴大小设置为第二大小。 所公开方法的一个优点是缓存片大小自适应地大小，导致用于较不复杂的渲染目标配置的较少高速缓存片。 自动调整高速缓存片段的大小可以提高处理器利用率并降低功耗。 另外，一个统一的L2高速缓存块允许缓存区块数据和其他数据之间的高速缓冲存储器的动态分区。

公开(公告)号：US08510531B1

公开(公告)日：2013-08-13

申请号：US13627320

申请日：2012-09-26

Applicant: Chet Haase ,  Raphael Linus Levien ,  Romain Guy

Inventor： Chet Haase ,  Raphael Linus Levien ,  Romain Guy

IPC: G06F12/00

CPC classification number: G06F12/0873 ,  G06F12/023 ,  G06F12/04 ,  G06F2212/455 ,  G06T1/60 ,  G09G5/393

Abstract: A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the top margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the top margin to start below the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.

Abstract translation: 用于存储信息的方法可以包括确定接收到的数据对象是否适合存储器位图中的多个空闲块中的特定一个。 多个空闲块中的每一个可以包括具有顶边距，底边距和预定宽度的存储位图的列。 如果接收的数据对象适合，则从多个空闲块的特定一个的顶部边缘开始，接收的数据对象可以存储在多个空闲块中的特定的一个中。 多个数据块中的特定一个可以通过移动顶部余量来重新调整大小，从而开始于存储的接收数据对象之下。 对于多个空闲块中的每一个，确定可以包括将接收到的数据对象的高度与每个空闲数据块的高度进行比较。

公开(公告)号：US12125124B1

公开(公告)日：2024-10-22

申请号：US18118251

申请日：2023-03-07

Applicant: Amazon Technologies, Inc.

Inventor： Kun Xu ,  Ron Diamant

IPC: G06T3/60 ,  G06F12/0862 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T3/606 ,  G06V10/94

CPC classification number: G06T1/60 ,  G06F12/0862 ,  G06N3/04 ,  G06N3/08 ,  G06T3/606 ,  G06F2212/455 ,  G06V10/95

Abstract: In one example, an apparatus comprises: a buffer memory; and a memory access circuit configured to: fetch, from a first memory, a set of first groups of data elements of a first matrix, each first group of data elements being stored at consecutive memory addresses at the first memory; based on a first configuration, store the set of first groups of data elements at consecutive memory addresses or at non-consecutive memory addresses at the buffer memory; based on a second configuration that defines a memory address offset, fetch a set of second groups of the data elements from the buffer memory, each second group of the data elements being stored at consecutive memory addresses of the buffer memory, each second group being separated by the memory address offset in the buffer memory; and store each fetched second group at consecutive addresses of a destination memory to form a second matrix.

公开(公告)号：US12093210B2

公开(公告)日：2024-09-17

申请号：US17430574

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Joydeep Ray ,  Mike Macpherson ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Jayakrishna P S ,  K Pattabhiraman ,  Sudhakar Kamma

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240184739A1

公开(公告)日：2024-06-06

申请号：US18432859

申请日：2024-02-05

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Niranjan COORAY ,  Subramaniam MAIYURAN ,  Altug KOKER ,  Prasoonkumar SURTI ,  Varghese GEORGE ,  Valentin ANDREI ,  Abhishek APPU ,  Guadalupe GARCIA ,  Pattabhiraman K ,  Sungye KIM ,  Sanjay KUMAR ,  Pratik MAROLIA ,  Elmoustapha OULD-AHMED-VALL ,  Vasanth RANGANATHAN ,  William SADLER ,  Lakshminarayanan STRIRAMASSARMA

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20240177264A1

公开(公告)日：2024-05-30

申请号：US18536581

申请日：2023-12-12

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Abhishek R. APPU ,  Altug KOKER ,  Balaji VEMBU

IPC: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0888 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0888 ,  G06T1/60 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/621

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

公开(公告)号：US11875427B2

公开(公告)日：2024-01-16

申请号：US17473754

申请日：2021-09-13

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Christopher P. Tann ,  Rohit K. Gupta

IPC: G06T1/60 ,  G06F12/0895 ,  G06F12/0873 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0873 ,  G06F12/0895 ,  G06T1/20 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/455

Abstract: An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

公开(公告)号：US20230195685A1

公开(公告)日：2023-06-22

申请号：US18170900

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06F15/78 ,  G06F9/30 ,  G06F12/128 ,  G06F17/16 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0866 ,  G06F7/544 ,  G06F9/50 ,  G06F17/18 ,  G06F9/38 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/0888 ,  G06F12/0802 ,  G06T1/60 ,  G06F12/0871 ,  G06T1/20 ,  H03M7/46 ,  G06F12/0875 ,  G06F12/0862 ,  G06F15/80 ,  G06F12/0897 ,  G06F12/0893 ,  G06F12/0804 ,  G06F12/0882 ,  G06F7/575 ,  G06F12/1009 ,  G06F12/0895 ,  G06F7/58 ,  G06T15/06 ,  G06N3/08

CPC classification number: G06F15/7839 ,  G06F9/30043 ,  G06F12/128 ,  G06F17/16 ,  G06F12/0811 ,  G06F12/0238 ,  G06F12/0866 ,  G06F9/30014 ,  G06F7/5443 ,  G06F9/5077 ,  G06F12/0246 ,  G06F17/18 ,  G06F9/3887 ,  G06F12/0891 ,  G06F12/0607 ,  G06F12/0888 ,  G06F12/0802 ,  G06T1/60 ,  G06F9/30079 ,  G06F12/0871 ,  G06F9/30036 ,  G06T1/20 ,  H03M7/46 ,  G06F12/0215 ,  G06F12/0875 ,  G06F12/0862 ,  G06F15/8046 ,  G06F9/30047 ,  G06F9/30065 ,  G06F12/0897 ,  G06F9/5011 ,  G06F12/0893 ,  G06F12/0804 ,  G06F12/0882 ,  G06F9/3001 ,  G06F7/575 ,  G06F12/1009 ,  G06F9/3004 ,  G06F12/0895 ,  G06F7/588 ,  G06F2212/401 ,  G06F2212/1044 ,  G06F9/3867 ,  G06F9/3818 ,  G06F9/3802 ,  G06F2212/455 ,  G06F2212/1021 ,  G06F2212/60 ,  G06F2212/1008 ,  G06T15/06 ,  G06N3/08 ,  G06F2212/302

Abstract: Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.

公开(公告)号：US11650928B2

公开(公告)日：2023-05-16

申请号：US17715734

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0895 ,  G06F12/126 ,  G06F12/02 ,  G06T1/60

CPC classification number: G06F12/0895 ,  G06F12/023 ,  G06F12/126 ,  G06T1/60 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/455 ,  G06F2212/604 ,  G06F2212/608

Abstract: A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

公开(公告)号：US20180300145A1

公开(公告)日：2018-10-18

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3887 ,  G06F12/0811 ,  G06F12/0855 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/455 ,  G06F2212/602 ,  G06F2212/6024 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.