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公开(公告)号：US09928914B2
公开(公告)日：2018-03-27
申请号：US15491708
申请日：2017-04-19
申请人： Intel Corporation
发明人： Feng Pan , Ramin Ghodsi
CPC分类号： G11C16/10 , G11C7/04 , G11C7/065 , G11C7/1072 , G11C7/22 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C16/28 , G11C16/32 , G11C16/3454 , G11C16/3459 , G11C16/349 , G11C2211/5644
摘要： A disclosed example determines programmed states of a plurality of memory cells based on a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cells; determines, based on the programmed states, first ones of the memory cells that do not satisfy a target threshold voltage; and performs the programming pass on the first ones of the memory cells.
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公开(公告)号：US09928902B2
公开(公告)日：2018-03-27
申请号：US15378397
申请日：2016-12-14
发明人： Joon-Soo Kwon , Seung-Cheol Han , Sang-Won Hwang
CPC分类号： G11C11/5628 , G06F3/0608 , G06F3/064 , G06F3/0652 , G06F3/0679 , G11C7/14 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/225 , G11C16/28 , G11C16/3445 , G11C16/3459
摘要： In a method of operating a storage device including at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, a boundary page of a first memory block among a plurality of memory blocks included in the at least one nonvolatile memory device is searched for, at least one clean page, in which data is not written, of the first memory block is searched for, a dummy program operation is performed on a portion of the boundary page and the at least one clean page, and an erase operation is performed on the first memory block.
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公开(公告)号：US09922705B1
公开(公告)日：2018-03-20
申请号：US15621222
申请日：2017-06-13
发明人： Vinh Diep , Xuehong Yu , Zhengyi Zhang , Yingda Dong
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C2216/28
摘要： A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel gradient near the select gate transistors is reduced when the voltages of the drain and source ends of a memory string are increased to an erase level which charges up the channel. In one approach, the voltage of the word line which is adjacent to a select gate line is temporarily increased. Another approach builds off the first approach by temporarily increasing the voltage of the select gate line at the same time as the increase in the word line voltage.
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公开(公告)号：US20180075917A1
公开(公告)日：2018-03-15
申请号：US15445987
申请日：2017-03-01
CPC分类号： G11C16/3459 , G06F3/0619 , G06F3/065 , G06F3/067 , G06F11/1451 , G06F11/1469 , G06F2201/84 , G11C7/1048 , G11C7/1087 , G11C7/1096 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2216/20
摘要： A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.
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公开(公告)号：US20180075902A1
公开(公告)日：2018-03-15
申请号：US15459542
申请日：2017-03-15
CPC分类号： G11C11/5642 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C29/52 , G11C2029/0411 , G11C2211/5642 , G11C2211/5643 , H03M13/2906
摘要： According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
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公开(公告)号：US20180074730A1
公开(公告)日：2018-03-15
申请号：US15448967
申请日：2017-03-03
发明人： Kazuki Inoue , Sho Kodama , Keiri Nakanishi
CPC分类号： G06F3/0619 , G06F3/0614 , G06F3/0616 , G06F3/0638 , G06F3/0659 , G06F3/0679 , G06F11/1012 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/52 , G11C2029/0411 , G11C2029/4402 , H03M13/356 , H03M13/6318
摘要： According to one embodiment, a control unit determines a first physical sector in which first data is to be written among a plurality of physical sectors based on first information that is based on a result of the first data translation and the device characteristics of the plurality of physical sectors. A write unit writes data for which a first data translation is performed into the first physical sector of a nonvolatile memory.
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公开(公告)号：US20180068728A1
公开(公告)日：2018-03-08
申请号：US15806543
申请日：2017-11-08
发明人： JI-SANG LEE , DONGHUN KWAK , DAESEOK BYEON , CHIWEON YOON
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.
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98.发明申请公开(公告)号：US20180067697A1
公开(公告)日：2018-03-08
申请号：US15605404
申请日：2017-05-25
申请人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
发明人： Donghwan Lee , Junjin Kong , Seongnam Kwon , Seungkyung Ro , Changkyu Seol , Hong Rak Son , Pilsang Yoon , Donggi Lee , Heewon Lee
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06N99/005 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A storage device may include a nonvolatile memory device, a buffer memory, and a controller. The controller may perform first accesses on the nonvolatile memory device using the buffer memory, collect access result information and access environment information of the first accesses in the buffer memory, and generate an access classifier that predicts a result of a second access to the nonvolatile memory device by performing machine learning based on the access result information and the access environment information collected in the buffer memory.
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公开(公告)号：US09911500B2
公开(公告)日：2018-03-06
申请号：US15131392
申请日：2016-04-18
发明人： Liang Pang , Pao-ling Koh , Jiahui Yuan , Charles Kwong , Yingda Dong
CPC分类号： G11C16/28 , G11C7/14 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C2211/5621
摘要： Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.
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公开(公告)号：US09911487B2
公开(公告)日：2018-03-06
申请号：US14754838
申请日：2015-06-30
申请人： EMC Corporation
CPC分类号： G11C11/5628 , G06F3/0611 , G06F3/0619 , G06F3/0644 , G06F3/0646 , G06F3/0679 , G06F3/0688 , G06F11/0727 , G06F11/0751 , G06F11/0793
摘要： Embodiments of the technology relate to storing user data and metadata in persistent storage in the event of a power failure and then recovering such stored data and metadata when power is restored.
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