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    HIGH TEMPERATURE TUNGSTEN METALLIZATION PROCESS
    92.
    发明申请
    HIGH TEMPERATURE TUNGSTEN METALLIZATION PROCESS 失效
    高温钨钢冶金工艺

    公开(公告)号：US20130109172A1

    公开(公告)日：2013-05-02

    申请号：US13660463

    申请日：2012-10-25

    申请人： JOSHUA COLLINS ,  Murali K. Narasimhan ,  Jingjing Liu ,  Sang-Hyeob Lee ,  Kai Wu ,  Avgerinos V. Gelatos

    发明人： JOSHUA COLLINS ,  Murali K. Narasimhan ,  Jingjing Liu ,  Sang-Hyeob Lee ,  Kai Wu ,  Avgerinos V. Gelatos

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76876 ,  H01L21/743 ,  H01L21/76814 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/53266 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide an improved process for depositing tungsten-containing materials. In one embodiment, the method for forming a tungsten-containing material on a substrate includes forming an adhesion layer containing titanium nitride on a dielectric layer disposed on a substrate, forming a tungsten nitride intermediate layer on the adhesion layer, wherein the tungsten nitride intermediate layer contains tungsten nitride and carbon. The method further includes forming a tungsten barrier layer (e.g., tungsten or tungsten-carbon material) from the tungsten nitride intermediate layer by thermal decomposition during a thermal annealing process (e.g., temperature from about 700° C. to less than 1,000° C.). Subsequently, the method includes optionally forming a nucleation layer on the tungsten barrier layer, optionally exposing the tungsten barrier layer and/or the nucleation layer to a reducing agent during soak processes, and forming a tungsten bulk layer on or over the tungsten barrier layer and/or the nucleation layer.

    摘要翻译： 本发明的实施方案提供了一种用于沉积含钨材料的改进方法。 在一个实施例中，在基板上形成含钨材料的方法包括在设置在基板上的电介质层上形成含有氮化钛的粘合层，在粘合层上形成氮化钨中间层，其中氮化钨中间层 含有氮化钨和碳。 该方法还包括在热退火过程中（例如，从约700℃至小于1000℃的温度）通过热分解从氮化钨中间层形成钨阻挡层（例如，钨或钨 - 碳材料） ）。 随后，该方法包括任选地在钨阻挡层上形成成核层，任选地在浸泡过程期间将钨阻挡层和/或成核层暴露于还原剂，以及在钨阻挡层上或之上形成钨体层，以及 /或成核层。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    93.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130099298A1

    公开(公告)日：2013-04-25

    申请号：US13350519

    申请日：2012-01-13

    申请人： Se Hyun KIM

    发明人： Se Hyun KIM

    IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L29/78

    CPC分类号： H01L29/42356 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894

    摘要： A semiconductor device comprises a buried gate formed in a mat and in an adjacent dummy region. A space larger than is conventional is formed in a dummy region of a mat edge where the buried gate is to be created. This larger space inhibits shortening of an end of a buried gate and reduction in pattern size attributable to lithographic distortion arising between patterned (mat) and unpatterned (dummy) regions. Device reliability is thereby improved by avoiding gap-fill defects of a gate material.

    摘要翻译： 半导体器件包括形成在垫中和相邻的虚拟区域中的掩埋栅极。 在要形成掩埋栅的垫边缘的虚拟区域中形成大于常规的空间。 这种更大的空间抑制了掩埋栅极的端部缩短，并且由于在图案化（垫）和未图案化（虚拟）区域之间产生的光刻变形而减小了图案尺寸。 从而通过避免栅极材料的间隙填充缺陷来改善器件的可靠性。

    Structure and method to integrate embedded DRAM with finfet
    94.
    发明授权
    Structure and method to integrate embedded DRAM with finfet 有权
    嵌入式DRAM与finfet的结构和方法

    公开(公告)号：US08421139B2

    公开(公告)日：2013-04-16

    申请号：US12755487

    申请日：2010-04-07

    申请人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

    发明人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/10826 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1211

    摘要： A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.

    摘要翻译： 晶体管包括第一鳍结构和形成在衬底上的至少第二鳍结构。 在第一和第二翅片结构之间形成深沟槽区域。 深沟槽区域延伸穿过衬底的绝缘体层和衬底的半导体层。 在深沟槽区域内形成高k金属栅极。 在与金属层相邻的深沟槽区域内形成多晶硅层。 多晶硅层和高k金属层凹陷在绝缘体层的顶表面下方。 深沟槽区域中的多晶带形成在高k金属栅极和多晶硅材料的顶部上。 该多晶带的尺寸被设计成在第一和第二鳍结构的顶表面下方。 第一翅片结构和第二翅片结构电耦合到多晶带。

    Concurrent memory bank access and refresh request queuing
    95.
    发明授权
    Concurrent memory bank access and refresh request queuing 有权
    并发存储器存取和刷新请求排队

    公开(公告)号：US08417883B2

    公开(公告)日：2013-04-09

    申请号：US13436381

    申请日：2012-03-30

    申请人： Robert J. Proebsting

    发明人： Robert J. Proebsting

    IPC分类号： G06F12/00

    CPC分类号： G11C11/40618 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/104 ,  G11C2207/229 ,  H01L27/10891 ,  H01L27/10897

    摘要： An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry configured to queue pending refresh requests for a plurality of memory banks; and second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank from the plurality of memory banks exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

    摘要翻译： 本文公开了与存储器相关联的装置和系统。 在各种实施例中，装置可以包括被配置为对多个存储体排队等待刷新请求的第一电路; 以及第二电路，其耦合到所述第一电路并且被配置为响应于对来自所述多个存储体的存储器组的排队等待刷新请求的数量超过预定数量的确定来设置刷新标志。 可以公开和/或要求保护其他实施例。

    Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making Same
    96.
    发明申请
    Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making Same 审中-公开
    具有DRAM字线和栅极电极的半导体器件在由金属组成的器件的非存储器区域中，以及制造相同的方法

    公开(公告)号：US20130049123A1

    公开(公告)日：2013-02-28

    申请号：US13215568

    申请日：2011-08-23

    申请人： Peter Baars ,  Christopher M. Prindle ,  Johannes F. Groschopf

    发明人： Peter Baars ,  Christopher M. Prindle ,  Johannes F. Groschopf

    IPC分类号： H01L27/088 ,  H01L21/28

    CPC分类号： H01L27/10891 ,  H01L27/10894 ,  H01L29/66545

    摘要： Generally, the present disclosure is directed to a semiconductor device with DRAM word lines and gate electrodes in a non-memory region of the device made of at least one layer of metal, and various methods of making such devices. One illustrative method disclosed herein involves forming a sacrificial gate electrode structure in a logic region of the device and a word line in a memory array of the device, wherein the sacrificial gate electrode structure and the word line have a first layer of insulating material and at least one first layer comprising a metal, removing the sacrificial gate electrode structure in the logic region to define a gate opening and forming a final gate electrode structure in the gate opening.

    摘要翻译： 通常，本公开涉及在由至少一层金属制成的器件的非存储器区域中的DRAM字线和栅电极的半导体器件以及制造这种器件的各种方法。 本文中公开的一种说明性方法包括在器件的逻辑区域和器件的存储器阵列中形成牺牲栅电极结构，其中牺牲栅电极结构和字线具有第一绝缘材料层 包括金属的至少一个第一层，去除逻辑区域中的牺牲栅电极结构以限定栅极开口并在栅极开口中形成最终的栅电极结构。

    Split word line fabrication process
    99.
    发明授权
    Split word line fabrication process 有权
    分割字线制作工艺

    公开(公告)号：US08377813B2

    公开(公告)日：2013-02-19

    申请号：US12870612

    申请日：2010-08-27

    申请人： Chih-Hao Lin

    发明人： Chih-Hao Lin

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/10891 ,  H01L21/3083 ,  H01L27/10876 ,  H01L29/66666

    摘要： A method for forming a buried split word line structure is provided. The method comprises the following steps. At first, a substrate having a trench therein is provided. Two liners are formed to a first thickness on sidewalls of the trench. Then, the trench is filled with a first insulating layer to a first height. The two liners are removed. Finally, a conductive material is deposited to a second height between and adjacent to the first insulating layer and the trench. Here, the first height is greater than the second height.

    摘要翻译： 提供了一种用于形成掩埋分割字线结构的方法。 该方法包括以下步骤。 首先，提供其中具有沟槽的衬底。 两个衬垫在沟槽的侧壁上形成为第一厚度。 然后，将沟槽填充到第一高度的第一绝缘层。 两个衬垫被移除。 最后，将导电材料沉积到第一绝缘层和沟槽之间的第二高度上并与其相邻。 这里，第一高度大于第二高度。