公开(公告)号：US07498632B2

公开(公告)日：2009-03-03

申请号：US11719934

申请日：2005-12-06

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/94

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7781 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/792

Abstract: The present invention relates to a nano-scale flash memory device having a saddle structure, and a fabrication method thereof. Particularly, the invention relates to a highly integrated, high-performance flash memory device having a saddle structure for improving the scaling-down characteristic and performance of the MOS-based flash memory device. According to the invention, a portion of an insulating film around a recessed channel is selectively removed to expose the surface and sides of the recessed channel. A tunneling insulating film is formed on the exposed surface and sides of the recessed channel. On the resulting structure, a floating electrode, an inter-electrode insulating film and a control electrode are formed, thus fabricating the device. Particularly when the floating electrode is made of an insulating nitride film or pluralities of nano-scale dots, an excellent memory device can be made without using an additional mask. According to the invention, the scaling-down characteristic of the device is excellent, and current drive capability can be greatly increased since a channel through which current can flow is formed on the surface and sides of the recessed channel. Also, the ability of the control electrode to control the channel can be enhanced, so that memory write/erase characteristics can be improved.

Abstract translation: 本发明涉及具有鞍座结构的纳米级闪存装置及其制造方法。 特别地，本发明涉及一种高度集成的高性能闪速存储器件，其具有用于提高基于MOS的闪存器件的缩小特性和性能的鞍形结构。 根据本发明，选择性地去除围绕凹槽的绝缘膜的一部分以露出凹槽的表面和侧面。 隧道绝缘膜形成在凹槽的暴露表面和侧面上。 在所得到的结构上，形成浮置电极，电极间绝缘膜和控制电极，从而制造该器件。 特别是当浮置电极由绝缘氮化物膜或多个纳米级点构成时，可以在不使用附加掩模的情况下制造优良的存储器件。 根据本发明，由于在凹槽的表面和侧面上形成电流可以流过的通道，所以器件的缩小特性是优异的，并且可以大大增加电流驱动能力。 而且，可以提高控制电极控制通道的能力，从而可以提高存储器写/擦除特性。

公开(公告)号：US07494940B2

公开(公告)日：2009-02-24

申请号：US11333741

申请日：2006-01-17

Applicant: Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/00

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

Abstract translation: 可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理， 或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。

公开(公告)号：US20090032966A1

公开(公告)日：2009-02-05

申请号：US12222004

申请日：2008-07-31

Applicant: Jong Ho Lee ,  Dong Ho Lee ,  Eun Chul Ahn ,  Yong Chai Kwon

Inventor： Jong Ho Lee ,  Dong Ho Lee ,  Eun Chul Ahn ,  Yong Chai Kwon

IPC: H01L23/52 ,  H01L21/00 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/525 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having an active surface, thinning the substrate by removing material from a second surface of the substrate opposite the active surface, bonding a metal carrier to the second surface of the thinned substrate, forming a via opening in the thinned substrate, forming a conductive member in the via opening, and patterning the metal carrier bonded to the second surface of the thinned substrate to form a metal pattern.

Abstract translation: 一种制造半导体器件的方法包括提供具有活性表面的半导体衬底，通过从衬底的与活性表面相对的第二表面去除材料来稀释衬底，将金属载体接合到薄化衬底的第二表面上，形成 通过在所述薄化基板中的开口，在所述通孔开口中形成导电构件，并且图案化结合到所述薄化基板的第二表面的金属载体以形成金属图案。

公开(公告)号：US20080290514A1

公开(公告)日：2008-11-27

申请号：US12154022

申请日：2008-05-20

Applicant: Young-Lyong Kim ,  Jong-Ho Lee ,  Chul-Yong Jang

Inventor： Young-Lyong Kim ,  Jong-Ho Lee ,  Chul-Yong Jang

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/562 ,  H01L29/0657 ,  H01L2221/6834 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: In a semiconductor device, a package including the semiconductor device and a method of forming the same, the semiconductor device package includes a semiconductor device, a wiring board, and an underfill material layer. The semiconductor device includes a semiconductor chip, a metal layer, and solder balls for bump contacts. The semiconductor chip includes an active surface having bonding pads and a rear surface opposite the active surface and having concave portions corresponding to the bonding pads. The metal layer fills the concave portions and covers the rear surface. The solder balls for bump contacts are provided on the bonding pads. The wiring board includes an upper surface to which the semiconductor device is mounted and a lower surface opposite the upper surface. The underfill material layer fills a space between the active surface of the semiconductor device and the upper surface of the wiring board. The semiconductor device and the wiring board are electrically connected to each other by the solder balls for bump contacts of the semiconductor device and bonding electrodes included in the upper surface of the wiring board.

Abstract translation: 在半导体器件中，包括半导体器件的封装及其形成方法，半导体器件封装包括半导体器件，布线板和底部填充材料层。 半导体器件包括半导体芯片，金属层和用于凸点接触的焊球。 半导体芯片包括具有接合焊盘的活动表面和与有源表面相对的后表面，并且具有对应于焊盘的凹部。 金属层填充凹部并覆盖后表面。 用于凸点触点的焊球设置在焊盘上。 布线板包括安装半导体器件的上表面和与上表面相对的下表面。 底部填充材料层填充半导体器件的有源表面和布线板的上表面之间的空间。 半导体器件和布线板通过用于半导体器件的凸起接触的焊球和布线板的上表面中包括的接合电极彼此电连接。

公开(公告)号：US20080283996A1

公开(公告)日：2008-11-20

申请号：US12121490

申请日：2008-05-15

Applicant: Min-Ho O ,  Jong-Ho LEE ,  Eun-Chul AHN ,  Pyoung-Wan KIM

Inventor： Min-Ho O ,  Jong-Ho LEE ,  Eun-Chul AHN ,  Pyoung-Wan KIM

IPC: H01L23/49 ,  H01L23/538

CPC classification number: H01L24/85 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.

Abstract translation: 提供了使用芯片嵌入式插入器基板的半导体封装。 芯片嵌入式插入器基板包括：包括多个芯片焊盘的芯片; 具有安装在其上的芯片并且包括用于重新分配芯片焊盘的多个再分配焊盘的衬底; 用于将芯片焊盘连接到再分配焊盘的接合线; 保护层，其具有用于在掩埋所述芯片和所述基板的同时露出所述再分布焊盘的通孔; 以及通过通孔连接到再分配焊盘的通孔。 包括各种尺寸的芯片的半导体封装使用芯片嵌入式插入器基板来制造。

公开(公告)号：US20080251825A1

公开(公告)日：2008-10-16

申请号：US12101143

申请日：2008-04-10

Applicant: Jong-Ho LEE

Inventor： Jong-Ho LEE

IPC: H01L29/78 ,  H01L27/108

CPC classification number: H01L29/42392 ,  G11C11/403 ,  H01L27/10876 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/78642 ,  H01L29/78648

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes a semiconductor pillar, a gate insulating layer formed on a portion of a surface of the semiconductor pillar, a gate electrode formed on the gate insulating layer, and source/drain regions formed on portions of the semiconductor pillar where the gate electrode is not formed, in which the gate electrode includes a first gate electrode, a second gate electrode, and an inter-gate insulating layer, in which the first gate electrode has a work function higher than that of the second gate electrode, in which the inter-gate insulating layer is formed between the first gate electrode and the second gate electrode, and in which the first gate electrode and the second gate electrode are electrically connected by a contact or a metal interconnection line. A portion of the second gate electrode having the work function lower than that of the first gate electrode is overlapped by the drain region. Accordingly, the gate electrode of the pillar-type FET is formed using a material having a high work function, so that the threshold voltage can be increased and the work function of the portion of the gate electrode overlapped by the drain region can be decreased. Therefore, gate induced drain leakage is reduced, so that off-state leakage current can likewise be greatly reduced.

Abstract translation: 提供了具有低泄漏电流的柱型场效应晶体管。 柱型场效应晶体管包括半导体柱，形成在半导体柱的表面的一部分上的栅极绝缘层，形成在栅极绝缘层上的栅极电极和形成在半导体柱的部分上的源极/漏极区域 其中栅电极不形成，其中栅电极包括第一栅电极，第二栅电极和栅间绝缘层，其中第一栅电极具有比第二栅电极高的功函数 其中，所述栅极绝缘层形成在所述第一栅电极和所述第二栅电极之间，并且所述第一栅电极和所述第二栅电极通过触点或金属互连线电连接。 具有比第一栅极电极功函数低的功函数的第二栅电极的一部分与漏区重叠。 因此，利用具有高功函数的材料形成柱型FET的栅电极，从而可以提高阈值电压，并且可以减小与漏极区重叠的部分栅极的功函数。 因此，栅极感应漏极泄漏减小，从而同样可以大大降低截止状态的漏电流。

公开(公告)号：US20080150036A1

公开(公告)日：2008-06-26

申请号：US11966640

申请日：2007-12-28

Applicant: HYUNG SUK JUNG ,  Jong-Ho Lee ,  Sung Kee Han ,  Ha Jin Lim

Inventor： HYUNG SUK JUNG ,  Jong-Ho Lee ,  Sung Kee Han ,  Ha Jin Lim

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/20 ,  H01L29/22 ,  H01L29/24 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a gate insulating layer formed on the semiconductor substrate, an NMOS gate formed on the gate insulating layer of the NMOS region, and a PMOS gate formed on the gate insulating layer of the PMOS region. Any one of the NMOS gate and the PMOS gate includes a one-layered conductive layer pattern, and another of the NMOS gate and the PMOS gate includes a three-layered conductive layer pattern.

Abstract translation: 半导体器件包括：包括NMOS区域和PMOS区域的半导体衬底;形成在半导体衬底上的栅极绝缘层;形成在NMOS区域的栅极绝缘层上的NMOS栅极;以及栅极绝缘层上形成的PMOS栅极; 的PMOS区域。 NMOS栅极和PMOS栅极中的任何一个包括单层导电层图案，NMOS栅极和PMOS栅极中的另一个包括三层导电层图案。

公开(公告)号：US07371633B2

公开(公告)日：2008-05-13

申请号：US11027256

申请日：2004-12-30

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L21/8238

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20080106487A1

公开(公告)日：2008-05-08

申请号：US11958206

申请日：2007-12-17

Applicant: Jong-ho LEE ,  Kwang-kee Lee ,  Sung-wook Byun ,  Glenn Adams ,  Un-gyo Jung

Inventor： Jong-ho LEE ,  Kwang-kee Lee ,  Sung-wook Byun ,  Glenn Adams ,  Un-gyo Jung

IPC: G09G5/00 ,  H04N5/45

CPC classification number: H04N5/45 ,  G09G5/14 ,  G09G5/30 ,  H04N5/44591 ,  H04N21/4316 ,  H04N21/4431 ,  H04N21/4622 ,  H04N21/482

Abstract: An apparatus and method for providing multiple screens are provided. The apparatus includes a service processing module which provides a plurality of services to which a plurality of audio contents are respectively allocated, an interface module which receives a command to designate a first audio content of the plurality of audio contents as an audio content to be focused, an output module which outputs the first audio content that focused in response to the received command.

Abstract translation: 提供了一种用于提供多个屏幕的装置和方法。 该装置包括提供分配了多个音频内容的多个服务的服务处理模块，接收将多个音频内容中的第一音频内容指定为要聚焦的音频内容的命令的接口模块 ，输出模块，其输出响应于所接收的命令而聚焦的第一音频内容。

公开(公告)号：US20080104988A1

公开(公告)日：2008-05-08

申请号：US11710574

申请日：2007-02-26

Applicant: Jong Ho Lee ,  Moon Shin Kim

Inventor： Jong Ho Lee ,  Moon Shin Kim

IPC: F25D21/14

CPC classification number: F24F1/025 ,  F24F13/222 ,  F24F2013/205 ,  F24F2013/227 ,  F24F2140/30

Abstract: An air conditioner is provided. The air conditioner according to an embodiment of the present invention includes: a base pan constituting a lower appearance: and a condensed water detector detecting the amount of condensed water collected on the base pan. The air conditioner according to another embodiment of the present invention includes: a base pan constituting a lower appearance; a blower unit provided at one side of the base pan to guide a flow of air; and a motor providing a fan with a rotational power, wherein a motor support supporting the motor is further installed on the base pan.

Abstract translation: 提供空调。 根据本发明实施例的空调器包括：底盘，其形状较低;以及冷凝水检测器，其检测在底盘上收集的冷凝水的量。 根据本发明的另一实施例的空调器包括：构成较低外观的底盘; 鼓风机单元，设置在底盘的一侧以引导空气流; 以及提供具有旋转动力的风扇的电动机，其中支撑电动机的电动机支架进一步安装在底盘上。