公开(公告)号：US07656742B2

公开(公告)日：2010-02-02

申请号：US12128464

申请日：2008-05-28

Applicant: Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

Inventor： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

IPC: G11C8/00

CPC classification number: G06F12/02 ,  G11C7/1078 ,  G11C7/109

Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

Abstract translation: 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US20100002471A1

公开(公告)日：2010-01-07

申请号：US12234245

申请日：2008-09-19

Applicant: Tae Won HEO ,  Gun Woo MOON ,  Woo Jin LEE ,  Ki Bum PARK ,  Don Sik KIM ,  Chong Eun KIM ,  Jong Pil KIM ,  Sang Cheol BONG ,  Hak Ryong KIM ,  Dong Joong KIM

Inventor： Tae Won HEO ,  Gun Woo MOON ,  Woo Jin LEE ,  Ki Bum PARK ,  Don Sik KIM ,  Chong Eun KIM ,  Jong Pil KIM ,  Sang Cheol BONG ,  Hak Ryong KIM ,  Dong Joong KIM

IPC: H02M3/335

CPC classification number: H02M3/33592 ,  H02M3/337 ,  H02M2007/4818 ,  H02M2007/53878 ,  Y02B70/1441 ,  Y02B70/1475

Abstract: A phase shift full bridge converter with a reduced current stress includes: a switching unit that switches an input voltage; a transformer that includes a first capacitor serially connected to, and having a primary side and a secondary side; an auxiliary circuit unit that includes a first switch, a second switch, and a second capacitor, which are connected in parallel to the secondary side of the transformer; and a rectification unit that is connected to the auxiliary circuit unit, with an output inductor being removed.

Abstract translation: 具有减小的电流应力的相移全桥转换器包括：切换输入电压的开关单元; 变压器，其包括串联连接到第一电容器并且具有初级侧和次级侧的第一电容器; 辅助电路单元，其包括与变压器的次级侧并联连接的第一开关，第二开关和第二电容器; 以及整流单元，其连接到辅助电路单元，其中输出电感器被去除。

公开(公告)号：US07643355B2

公开(公告)日：2010-01-05

申请号：US11896722

申请日：2007-09-05

Applicant: Joung-Yeal Kim ,  Jeong-Don Lim ,  Sung-Hoon Kim ,  Woo-Jin Lee

Inventor： Joung-Yeal Kim ,  Jeong-Don Lim ,  Sung-Hoon Kim ,  Woo-Jin Lee

IPC: G11C7/00

CPC classification number: G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096 ,  G11C2207/107

Abstract: According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.

Abstract translation: 根据示例实施例，半导体存储器件可以包括存储器芯，输入电路和/或输出电路。 输入电路可以被配置为使用响应于在不同周期期间启用的输入控制信号而工作的锁存电路从第一数据产生第二数据。 输入电路还可以被配置为向存储器核提供第二数据。 第二数据可以具有2N次第一数据的比特数，其中N是正整数。 输出电路可以被配置为使用响应于在不同周期期间启用的输出控制信号而工作的锁存电路从第三数据生成第四数据。 输出电路还可以被配置为向数据输出引脚提供第四数据。 第四数据可以具有第三数据的比特数的1/2N倍。 还提供了一种输入/输出数据的方法。

公开(公告)号：US20090267813A1

公开(公告)日：2009-10-29

申请号：US12453109

申请日：2009-04-29

Applicant: Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

Inventor： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC: H03M7/00

CPC classification number: H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract translation: 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特顺序进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20090180733A1

公开(公告)日：2009-07-16

申请号：US12350978

申请日：2009-01-09

Applicant: Sung Hwan HWANG ,  Byung Sup Rho ,  Jung Woon Lim ,  Woo Jin Lee

Inventor： Sung Hwan HWANG ,  Byung Sup Rho ,  Jung Woon Lim ,  Woo Jin Lee

IPC: G02B6/12 ,  H01L23/552

CPC classification number: G02B6/43 ,  G02B6/4214 ,  H01L23/367 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15192 ,  H01L2924/3511 ,  H05K1/0274 ,  H05K3/4691

Abstract: A system package using flexible optical waveguides and electrical wires, and a signal processing method thereof are disclosed. Several rigid substrates having highly integrated electronic elements and optical elements mounted thereon can be electrically and optically connected by using flexible substrates that are electrically wired and optically connected. The package can be variously changed when configuring the package by the flexible substrate and the heat dissipation device and the electromagnetic shielding device are installed in the inside of the package, making it possible to solve electromagnetic wave interference problems and thermal problems occurring in the inside of the package.

Abstract translation: 公开了一种使用柔性光波导和电线的系统封装及其信号处理方法。 具有高度集成的电子元件和安装在其上的光学元件的几个刚性基板可以通过使用电连接和光学连接的柔性基板电连接和光学连接。 当通过柔性基板构造封装时，可以对封装进行各种改变，并且散热装置和电磁屏蔽装置安装在封装的内部，使得可以解决电磁波干扰问题和在内部发生的热问题 包装。

公开(公告)号：US07470623B2

公开(公告)日：2008-12-30

申请号：US11493126

申请日：2006-07-26

Applicant: Woo Jin Lee

Inventor： Woo Jin Lee

IPC: H01L21/302 ,  C09K13/00

CPC classification number: H01L21/3212 ,  C09G1/04

Abstract: A solution for platinum chemical mechanical polishing is disclosed. Further, a method for forming Pt patterns is disclosed which utilizes the disclosed Pt-CMP solution which contains an alkali aqueous solution and an oxidizer which improves the polishing rate and polishing characteristics of Pt which forms a lower electrode of a metal capacitor.

Abstract translation: 公开了铂化学机械抛光的解决方案。 此外，公开了一种用于形成Pt图案的方法，其利用所公开的含有碱性水溶液的Pt-CMP溶液和提高形成金属电容器的下电极的Pt的抛光速率和抛光特性的氧化剂。

公开(公告)号：US07463072B2

公开(公告)日：2008-12-09

申请号：US11566651

申请日：2006-12-04

Applicant: Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

Inventor： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

IPC: H03B1/00

CPC classification number: H03K19/0013 ,  H03K19/018521

Abstract: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

Abstract translation: 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。

公开(公告)号：US20080225626A1

公开(公告)日：2008-09-18

申请号：US12128464

申请日：2008-05-28

Applicant: Hyun-Jin KIM ,  Seong-Jin JANG ,  Jeong-Don LIM ,  Kwang-Il PARK ,  Ho-Young SONG ,  Woo-Jin LEE

Inventor： Hyun-Jin KIM ,  Seong-Jin JANG ,  Jeong-Don LIM ,  Kwang-Il PARK ,  Ho-Young SONG ,  Woo-Jin LEE

IPC: G11C8/10

CPC classification number: G06F12/02 ,  G11C7/1078 ,  G11C7/109

Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

Abstract translation: 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

公开(公告)号：US20080075408A1

公开(公告)日：2008-03-27

申请号：US11737255

申请日：2007-04-19

Applicant: In Kui CHO ,  Woo Jin LEE ,  Sang Pil HAN ,  Seung Ho AHN ,  Gyung Ock KIM ,  Hee Kyung Sung

Inventor： In Kui CHO ,  Woo Jin LEE ,  Sang Pil HAN ,  Seung Ho AHN ,  Gyung Ock KIM ,  Hee Kyung Sung

IPC: G02B6/43

CPC classification number: G02B6/43 ,  G02B6/2552 ,  G02B6/4202 ,  G02B6/4239 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a method and structure for optical connection between an optical transmitter and an optical receiver. The method includes the steps of: forming on a substrate a light source device, an optical detection device, an optical transmission unit electrically connected with the light source device, and an optical detection unit electrically connected with the optical detection device; preparing a flexible optical transmission-connection medium to optically connect the light source device with the optical detection device; cutting the prepared optical transmission-connection medium and surface-finishing it; and connecting one end of the surface-finished optical transmission-connection medium with the light source device and the other end with the optical detection device. Fabrication of an optical package having a 3-dimensional structure is facilitated and fabrication time is reduced, thus improving productivity. In addition, since the optical transmission-connection medium is directly connected with the light source device and the optical detection device, a polishing operation or additional connection block is not required, thus facilitating mass production.

Abstract translation: 提供了一种用于光发射机和光接收机之间的光连接的方法和结构。 该方法包括以下步骤：在基板上形成光源装置，光检测装置，与光源装置电连接的光传输单元以及与该光检测装置电连接的光检测单元; 准备柔性光传输连接介质以将光源装置与光学检测装置光学连接; 切割准备的光传输连接介质并进行表面处理; 并且将表面光整传输连接介质的一端与光源装置连接，另一端与光学检测装置连接。 促进了具有3维结构的光学封装的制造，并减少了制造时间，从而提高了生产率。 此外，由于光传输连接介质与光源装置和光学检测装置直接连接，因此不需要抛光操作或附加连接块，因此便于批量生产。

公开(公告)号：US06987407B2

公开(公告)日：2006-01-17

申请号：US10744215

申请日：2003-12-22

Applicant: Dae-hyun Chung ,  Sang-woong Shin ,  Woo-jin Lee

Inventor： Dae-hyun Chung ,  Sang-woong Shin ,  Woo-jin Lee

IPC: H03L7/06

CPC classification number: G11C7/1066 ,  G11C7/1051 ,  G11C7/222 ,  H03L7/0812

Abstract: A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response to the phase error signal. A variable delay circuit is configured to change a delay time in response to the predetermined control signal, delay the phase of the external clock signal with respect to the changed delay time, lock the delayed external clock signal and output the internal clock signal. A compensation delay circuit is configured to receive a control voltage based on a delay time introduced by a data output circuit and delay a phase of the internal clock signal for a first delay time based on the control voltage and output the delayed internal clock signal to the phase detector. Methods of compensating a delay for a DLL are also provided.

Abstract translation: 提供了延迟锁定环（DLL），其包括被配置为检测内部时钟信号和外部时钟信号之间的相位误差并输出相位误差信号的相位检测器。 低通滤波器被配置为响应于相位误差信号输出预定的控制信号。 可变延迟电路被配置为响应于预定控制信号改变延迟时间，相对于改变的延迟时间延迟外部时钟信号的相位，锁定延迟的外部时钟信号并输出​​内部时钟信号。 补偿延迟电路被配置为基于由数据输出电路引入的延迟时间接收控制电压，并且基于控制电压延迟内部时钟信号的第一延迟时间的相位，并将延迟的内部时钟信号输出到 相位检测器。 还提供了补偿DLL的延迟的方法。