公开(公告)号：US11901400B2

公开(公告)日：2024-02-13

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC: H01L49/02 ,  H01G4/012 ,  H01G4/30 ,  H01L23/522 ,  H10B51/00

CPC classification number: H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US11818963B2

公开(公告)日：2023-11-14

申请号：US17578093

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Kaan Oguz ,  Chia-Ching Lin ,  Christopher Wiegand ,  Tanay Gosavi ,  Ian Young

IPC: H10N50/80 ,  H01F10/32 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01F10/329 ,  H01F10/3268 ,  H01F10/3286 ,  H10B61/22 ,  H10N50/85

Abstract: An apparatus is provided which comprises: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device, wherein the first structure has a first dimension along the x-y plane and a second dimension in the z-plane, wherein the second dimension is substantially greater than the first dimension. The magnetic junction includes a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; and an interconnect adjacent to the third structure, wherein the interconnect comprises a spin orbit material.

公开(公告)号：US20230320230A1

公开(公告)日：2023-10-05

申请号：US17709074

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  H01L27/22

CPC classification number: H01L43/10 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14 ,  H01L27/228 ,  H03K19/18

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

公开(公告)号：US20230317847A1

公开(公告)日：2023-10-05

申请号：US17711665

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Hai Li ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Julien Sebot ,  Raseong Kim ,  Chia-Ching Lin ,  Punyashloka Debashis

IPC: H01L29/78 ,  H01L43/10

CPC classification number: H01L29/78391 ,  H01L43/10

Abstract: Technologies for majority gates are disclosed. In one embodiment, a ferroelectric layer has three inputs and an output adjacent a surface of the ferroelectric. When a voltage is applied to each input, the inputs and a ground plane below the ferroelectric layer form a capacitor. The ferroelectric layer becomes polarized based on the applied voltages at the inputs. The portion of the ferroelectric layer near the output becomes polarized in the direction of polarization of the majority of the inputs. The output voltage then reflects the majority voltage of the inputs.

公开(公告)号：US11742407B2

公开(公告)日：2023-08-29

申请号：US16700757

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Sou-Chi Chang ,  Devin Merrill ,  I-Cheng Tung ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Ian A. Young ,  Matthew V. Metz ,  Uygar E. Avci ,  Chia-Ching Lin ,  Owen Loh ,  Shriram Shivaraman ,  Eric Charles Mattson

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/512 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7851

Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack. A selector element is above the metal layer.

公开(公告)号：US20230253476A1

公开(公告)日：2023-08-10

申请号：US17666627

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Abhishek A. Sharma ,  Matthew V. Metz ,  Kaan Oguz ,  Urusa Shahriar Alaan ,  Scott B. Clendenning ,  Van H. Le ,  Chia-Ching Lin ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/06 ,  H01L27/108 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/517 ,  H01L29/42392 ,  H01L29/0673 ,  H01L27/10826 ,  H01L29/785 ,  H01L29/4966 ,  H01L29/41775

Abstract: Described herein are transistor devices formed using perovskite gate dielectrics. In one example, a transistor includes a high-k perovskite dielectric material between a gate electrode and a thin film semiconductor channel. In another example, four-terminal transistor includes a semiconductor channel, a gate stack that includes a perovskite dielectric layer on one side of the channel, and a body electrode on an opposite side of the channel. The body electrode adjusts a threshold voltage of the transistor.

公开(公告)号：US20230200081A1

公开(公告)日：2023-06-22

申请号：US17557119

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  John J. Plombon ,  Dmitri E. Nikonov ,  Kevin P. O'Brien ,  Ian A. Young ,  Matthew V. Metz ,  Chia-Ching Lin ,  Scott B. Clendenning ,  Punyashloka Debashish ,  Carly Lorraine Rogan ,  Brandon Jay Holybee ,  Kaan Oguz

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Described herein are integrated circuit devices formed using perovskite materials. Perovskite materials with a similar crystal structure and different electrical properties can be layered to realize a transistor or memory device. In some embodiments, a ferroelectric perovskite can be incorporated into a device with other perovskite films to form a ferroelectric memory device.

公开(公告)号：US20230189659A1

公开(公告)日：2023-06-15

申请号：US17550663

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Tanay A. Gosavi ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  Marko Radosavljevic ,  Ian Alexander Young

IPC: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14

CPC classification number: H01L43/02 ,  H01L43/04 ,  H01L43/10 ,  H01L43/12 ,  H01L43/14 ,  G06F7/58

Abstract: A probabilistic bit (p-bit) comprises a magnetic tunnel junction (MTJ) comprising a free layer whose magnetization orientation randomly fluctuates in the presence of thermal noise. The p-bit MTJ comprises a reference layer, a free layer, and an insulating layer between the reference and free layers. The reference layer and the free layer comprise synthetic antiferromagnets. The use of a synthetic antiferromagnet for the reference layer reduces the amount of stray magnetic field that can impact the magnetization of the free layer and the use of a synthetic antiferromagnet for the free layer reduces stray magnetic field bias on p-bit random number generation. Tuning the thickness of the nonmagnetic layer of synthetic antiferromagnet free layer can result in faster random number generation time relative to a comparable MTJ with a free layer comprising a single-layer ferromagnet.

公开(公告)号：US11640984B2

公开(公告)日：2023-05-02

申请号：US16363952

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Uygar Avci ,  Chia-Ching Lin ,  Owen Loh ,  Seung Hoon Sung ,  Aditya Kasukurti ,  Sou-Chi Chang ,  Tanay Gosavi ,  Ashish Verma Penumatcha

IPC: H01L29/51 ,  H01L29/78

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

公开(公告)号：US20230065198A1

公开(公告)日：2023-03-02

申请号：US17465752

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Kaan Oguz ,  Punyashloka Debashis

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/02 ,  H01L43/06 ,  H01L43/10 ,  G11C11/16 ,  G11C11/18 ,  H01F10/32

Abstract: A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.