公开(公告)号：US20240282620A1

公开(公告)日：2024-08-22

申请号：US18649986

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/74 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/498 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L21/743 ,  H01L21/26513 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/49816 ,  H01L29/66568 ,  H01L29/78 ,  H10B12/485 ,  H01L27/0694 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H10B12/09

Abstract: Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

公开(公告)号：US20240136295A1

公开(公告)日：2024-04-25

申请号：US18400745

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L27/0688 ,  H01L27/092

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US20240079369A1

公开(公告)日：2024-03-07

申请号：US17938917

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Bret K. Street ,  Wei Zhou ,  Kyle K. Kirby ,  Amy R. Griffin ,  Thiagarajan Raman ,  Jaekyu Song

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L24/16 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48145 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240072004A1

公开(公告)日：2024-02-29

申请号：US18237259

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L28/60 ,  H01L25/18 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/04642 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/059

Abstract: A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first layer of dielectric material at which a first portion of conductive material implementing a first portion of a passive circuit component is at least partially disposed. The second semiconductor die includes a second layer of dielectric material at which a second portion of conductive material implementing a second portion of the passive circuit component is at least partially disposed. A first contact pad at the first layer of dielectric material and a second contact pad at a second layer of dielectric material are coupled to create an interconnect electrically coupling the first semiconductor die and the second semiconductor die. A metal-metal bond is formed between the first portion of the passive circuit component and the second portion of the passive circuit component to create the passive circuit component.

公开(公告)号：US20240071987A1

公开(公告)日：2024-02-29

申请号：US17898356

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Bang-Ning Hsu ,  Kyle K. Kirby ,  Byung Hoon Moon

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/80222 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor die is provided, comprising a semiconductor substrate, a dielectric layer over the semiconductor substrate, a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate, and a region including a plurality of embedded nanoparticles in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the plurality of embedded nanoparticles to an externally-applied field.

公开(公告)号：US20240063207A1

公开(公告)日：2024-02-22

申请号：US17892038

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Terrence B. McDaniel ,  Amy R. Griffin ,  Kyle K. Kirby ,  Thiagarajan Raman

IPC: H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/34 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/568 ,  H01L24/11 ,  H01L24/80 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/345 ,  H01L23/3135 ,  H01L2221/68381 ,  H01L2221/68368 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/80006

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

公开(公告)号：US20240055400A1

公开(公告)日：2024-02-15

申请号：US17884475

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Kyle K. Kirby ,  Wei Zhou ,  Thiagarajan Raman

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

公开(公告)号：US11817305B2

公开(公告)日：2023-11-14

申请号：US17325122

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Systems and methods for a semiconductor device having a front-end-of-line structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor substrate material and a front side, and an interconnect structure extending through the dielectric material. The interconnect structure may be electrically connected to a semiconductor memory array proximate the front side of the dielectric material. The semiconductor device may further have an insulating material encasing at least a portion of the semiconductor memory array and an opening created during back-end-of-line processing through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.

公开(公告)号：US11735528B2

公开(公告)日：2023-08-22

申请号：US17588694

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/538 ,  G11C5/02 ,  G11C5/06 ,  H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5384 ,  G11C5/025 ,  G11C5/06 ,  H01L21/50 ,  H01L21/76877 ,  H01L23/5385 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor memory stack connected to a processing unit, and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack may include one or more memory dies attached to and carried by a memory controller die—e.g., high-bandwidth memory. Further, a processing unit (e.g., a processor) may be attached to the memory controller die without an interposer to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. In addition, the semiconductor memory stack and the processing unit can be attached to a package substrate without an interposer.

公开(公告)号：US20230238300A1

公开(公告)日：2023-07-27

申请号：US17583038

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Kyle K. Kirby

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/544 ,  H01L21/56 ,  H01L25/16 ,  H01L21/603

CPC classification number: H01L23/3736 ,  H01L23/3107 ,  H01L23/544 ,  H01L21/568 ,  H01L21/561 ,  H01L25/16 ,  H01L21/603

Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.