公开(公告)号：US10163771B2

公开(公告)日：2018-12-25

申请号：US15231512

申请日：2016-08-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu ,  Jonghae Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L25/00 ,  H01L27/092 ,  H01L49/02 ,  H01L23/48

Abstract: In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.

公开(公告)号：US10141908B2

公开(公告)日：2018-11-27

申请号：US15240987

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil Mudakatte ,  David Francis Berdy ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Shiqun Gu ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H03H1/00 ,  H03H7/01 ,  H03H7/46 ,  H01L49/02 ,  H05K1/16 ,  H05K1/03

Abstract: A passive device may include an inductor having interconnected trace segments. The passive device may also include parallel plate capacitors. Each of the plurality of parallel plate capacitors may have a dielectric layer between a pair of conductive plates. The parallel plate capacitors may not overlap more than one of the interconnected trace segments.

公开(公告)号：US10103135B2

公开(公告)日：2018-10-16

申请号：US15275068

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Jonghae Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu

IPC: H01L27/01 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/552 ,  H03H7/01 ,  H03H7/46 ,  H04B1/00 ,  H01L23/00

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

公开(公告)号：US20180177052A1

公开(公告)日：2018-06-21

申请号：US15896959

申请日：2018-02-14

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K1/18 ,  H03H7/01 ,  H05K3/10 ,  H05K3/30 ,  H05K3/40 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28

CPC classification number: H05K1/181 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/10 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/09227 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10962 ,  H05K2201/2036

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US09930783B2

公开(公告)日：2018-03-27

申请号：US15079811

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K7/00 ,  H05K1/18 ,  H03H7/01 ,  H05K3/30 ,  H05K3/40 ,  H05K3/10 ,  H05K1/11 ,  H05K1/14 ,  H01L23/12 ,  H01L21/56 ,  H01L23/15 ,  H01L23/28

CPC classification number: H05K1/181 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/10 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/09227 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10962 ,  H05K2201/2036

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US20180061775A1

公开(公告)日：2018-03-01

申请号：US15253782

申请日：2016-08-31

Applicant: QUALCOMM Incorporated

Inventor： Mario Velez ,  Niranjan Sunil Mudakatte ,  Changhan Yun ,  David Berdy ,  Shiqun Gu ,  Jonghae Kim ,  Chengjie Zuo

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A device that includes a single substrate layer, a plurality of interconnects over the single substrate layer, the plurality of interconnects configured to operate as at least one passive component, a first die coupled to the single substrate layer and the plurality of interconnects, and an encapsulation layer that at least partially encapsulates the first die and the plurality of interconnects configured to operate as at least one passive component. In some implementations, the single substrate layer, the first die and the encapsulation layer comprise an overall thickness of about 225 microns (μm) or less. In some implementations, the single substrate layer comprises a thickness of about 75 microns (μm) or less.

公开(公告)号：US20180040547A1

公开(公告)日：2018-02-08

申请号：US15231512

申请日：2016-08-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Shiqun Gu ,  Jonghae Kim

IPC: H01L23/498 ,  H01L27/092 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76264 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L27/092 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/08146 ,  H01L2224/08237 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/80013 ,  H01L2224/80047 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8285 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06572 ,  H01L2224/80001 ,  H01L2924/00014 ,  H01L21/76898

Abstract: In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.

公开(公告)号：US09876513B2

公开(公告)日：2018-01-23

申请号：US15088019

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H04B1/00 ,  H03H7/01 ,  H03H3/00

CPC classification number: H04B1/0057 ,  H01L2224/11 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  H03H2001/0085

Abstract: A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.

公开(公告)号：US09666362B2

公开(公告)日：2017-05-30

申请号：US15046302

申请日：2016-02-17

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01F5/00 ,  H01F41/04 ,  H01F27/28 ,  H01F27/29 ,  H01F17/00 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

公开(公告)号：US09620463B2

公开(公告)日：2017-04-11

申请号：US14634148

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  David Francis Berdy ,  Mario Francisco Velez ,  Changhan Hobie Yun ,  Chengjie Zuo ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L23/552 ,  H01L23/60 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/60 ,  H01L21/568 ,  H01L23/538 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/04105

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package (FOWLP) module or device. Intra-module shielding between individual chips within the FOWLP module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a FOWLP to ensure reliable grounding.