公开(公告)号：US09263343B2

公开(公告)日：2016-02-16

申请号：US14327343

申请日：2014-07-09

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L29/161 ,  H01L27/092 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/161 ,  H01L29/6656

Abstract: Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.

Abstract translation: 在集成电路中，在n型和p型区域上形成邻近栅电极的硅锗区。 通过光刻图案化的硬掩模即使在栅电极上的侧壁间隔物上的硬掩模的残留物上，也可以在p型区域上保护结构，同时从n型区域上选择性地除去硅锗。 锗栅极外延生长硅代替去除的硅锗，并且在去除p型区域结构之前的剩余硬掩模之前进行源极/漏极延伸植入。

公开(公告)号：US09257450B2

公开(公告)日：2016-02-09

申请号：US14182632

申请日：2014-02-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  James Kuss

IPC: H01L29/16 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming, above a substrate, a stack of alternating layers of first and second semiconductor materials. The second semiconductor material may be different than the first semiconductor material. The method may further include forming fins from the stack, with each fin having alternating layers of the first and second semiconductor materials, and selectively removing sidewall portions of the second semiconductor material from the fins to define recesses therein. The method may also include forming a dielectric material within the recesses, forming additional first semiconductor material on sidewall portions of the first semiconductor material in the fins, and forming a dielectric layer overlying the fins to define nanowires including the first semiconductor material within the dielectric layer.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成第一和第二半导体材料的交替层叠。 第二半导体材料可以不同于第一半导体材料。 该方法还可以包括从堆叠形成翅片，其中每个翅片具有第一和第二半导体材料的交替层，并且从翅片选择性地去除第二半导体材料的侧壁部分以在其中限定凹部。 该方法还可以包括在凹槽内形成介电材料，在鳍片中的第一半导体材料的侧壁部分上形成附加的第一半导体材料，以及形成覆盖鳍片的介电层，以限定纳米线，该纳米线包括介电层内的第一半导体材料 。

公开(公告)号：US20150348851A1

公开(公告)日：2015-12-03

申请号：US14822959

申请日：2015-08-11

Applicant: STMicroelectronics, Inc.

Inventor： Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/84 ,  H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract translation: 将半导体材料图案化以限定与底层基板绝缘的细长翅片。 多晶硅半导体材料沉积在细长翅片之上并在细长翅片之间，并且被图案化以限定延伸到在晶体管沟槽处垂直交叉在细长翅片上的细长门。 侧壁间隔件形成在细长门的侧壁上。 位于细长门之间的细长翅片的部分与下面的绝缘体一起被去除以暴露下面的基底。 然后在细长门之间的位置从下面的衬底外延生长一个或多个半导体材料层。 一个或多个半导体材料层可以包括未掺杂的外延层和上覆的掺杂外延层。 外延材料限定晶体管的源极或漏极。

公开(公告)号：US09190517B2

公开(公告)日：2015-11-17

申请号：US14518590

申请日：2014-10-20

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  Douglas Latulipe ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。

公开(公告)号：US20150303218A1

公开(公告)日：2015-10-22

申请号：US14253904

申请日：2014-04-16

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Sylvain Maitrejean ,  Romain Wacquez

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L21/266 ,  H01L21/306 ,  H01L21/84

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

Abstract translation: 描述了在衬底上的半导体层中形成局部的，不同应变的区域的方法和结构。 可以对原始半导体层中的初始的，无约束的绝缘体上半导体衬底进行处理以形成不同应变的区域。 不同应变区域可能具有相反类型的应变。 不同区域中的菌株可以独立形成。

公开(公告)号：US20150249153A1

公开(公告)日：2015-09-03

申请号：US14194215

申请日：2014-02-28

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10879 ,  H01L21/2251 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract translation: 描述了形成基底的局部应变区域的方法和结构。 可以在衬底的局部区域的边界处形成沟槽。 局部区域的侧壁的上部可以被覆盖层覆盖，并且局部区域的侧壁的下部可能不被覆盖。 可以将转换材料形成为与局部区域的下部接触，并且加热衬底。 加热可以将化学物质从转化材料引入下部，这在局部区域中产生应力。 这些方法可以用于形成应变通道的finFET。

公开(公告)号：US09123809B2

公开(公告)日：2015-09-01

申请号：US14494979

申请日：2014-09-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US09082788B2

公开(公告)日：2015-07-14

申请号：US13906702

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Huiming Bu

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of making a semiconductor device includes forming an intermediate structure including second semiconductor fin portions above a first semiconductor layer, and top first semiconductor fin portions extending from respective ones of the second semiconductor fin portions. The second semiconductor fin portions are selectively etchable with respect to the top first semiconductor fin portions. A dummy gate is on the intermediate structure. The second semiconductor fin portions are selectively etched to define bottom openings under respective ones of the top first semiconductor fin portions. The bottom openings are filled with a dielectric material.

Abstract translation: 制造半导体器件的方法包括在第一半导体层之上形成包括第二半导体鳍部的中间结构以及从第二半导体鳍部中的相应半导体鳍部延伸的顶部第一半导体鳍部。 第二半导体鳍片部分相对于顶部第一半导体鳍片部分可选择性地蚀刻。 虚拟门在中间结构上。 选择性地蚀刻第二半导体鳍片部分以在顶部第一半导体鳍片部分的相应一个下限定底部开口。 底部开口填充有电介质材料。

公开(公告)号：US09006816B2

公开(公告)日：2015-04-14

申请号：US13852645

申请日：2013-03-28

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Prasanna Khare ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack. The gate stack may include a first dielectric layer over the channel region, a first diffusion barrier layer over the first dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second dielectric layer over the first electrically conductive layer, a second diffusion barrier layer over the second dielectric layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域和栅极堆叠。 栅极堆叠可以包括沟道区域上的第一介电层，第一介电层上的第一扩散阻挡层，第一扩散阻挡层上的第一导电层，第一导电层上的第二介电层，第二介电层 第二介电层上的扩散阻挡层，以及位于第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US08952420B1

公开(公告)日：2015-02-10

申请号：US13953551

申请日：2013-07-29

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract translation: 描述形成应变通道鳍状FET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 可以将第一薄外延层切割并用于通过弹性弛豫向finFET的相邻沟道区施加应变。 该结构表现出优选的设计范围，用于增加应变在翅片高度上的诱导应变和均匀性。