公开(公告)号：US20250056786A1

公开(公告)日：2025-02-13

申请号：US18723731

申请日：2022-12-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Ryota HODO ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: H10B12/00

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor; the transistor includes an oxide, a first conductor and a second conductor over the oxide, a first insulator that is placed over the first conductor and the second conductor and includes a first opening and a second opening, a second insulator in the first opening of the first insulator, and a third conductor over the second insulator; the first opening in the first insulator includes a region overlapping with the oxide; the third conductor includes a region overlapping with the oxide with the second insulator therebetween; the capacitor includes the second conductor, a third insulator in the second opening of the first insulator, and a fourth conductor over the third insulator; and the distance between the first conductor and the second conductor is smaller than the width of the first opening in a cross-sectional view of the transistor in a channel length direction.

公开(公告)号：US20250008721A1

公开(公告)日：2025-01-02

申请号：US18706096

申请日：2022-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Rihito WADA ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: H10B12/00

Abstract: A small semiconductor device is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a p-channel first transistor containing silicon in a channel formation region. The second layer includes an n-channel second transistor containing a metal oxide in a channel formation region. The first transistor and the second transistor form a CMOS circuit. A channel length of the first transistor is longer than a channel length of the second transistor.

公开(公告)号：US20240402994A1

公开(公告)日：2024-12-05

申请号：US18683540

申请日：2022-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Tatsuya ONUKI ,  Atsushi MIYAGUCHI ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI

IPC: G06F7/523 ,  G06F7/50 ,  G11C11/405 ,  H10B12/00

Abstract: An electronic device with a novel structure is provided. In an electronic device including a semiconductor device, the semiconductor device includes a CPU, an accelerator, and a memory device. The CPU includes a scan flip-flop circuit and a backup circuit electrically connected to the scan flip-flop circuit. The backup circuit includes a first transistor. The accelerator includes an arithmetic circuit and a data retention circuit electrically connected to the arithmetic circuit. The data retention circuit includes a second transistor. The memory device includes a memory cell including a third transistor. The first transistor to the third transistor each include a semiconductor layer containing a metal oxide in a channel formation region.

公开(公告)号：US20240284674A1

公开(公告)日：2024-08-22

申请号：US18586866

申请日：2024-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H10B43/27 ,  H01L29/24 ,  H01L29/51 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L29/24 ,  H01L29/513

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US20230397447A1

公开(公告)日：2023-12-07

申请号：US18235995

申请日：2023-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1225 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/7869 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/78693 ,  H01L29/78696 ,  G11C2211/4016 ,  H01L21/8221

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20230369342A1

公开(公告)日：2023-11-16

申请号：US18224224

申请日：2023-07-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi KATO ,  Masayuki SAKAKURA

IPC: H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L27/1225 ,  H01L29/7869 ,  H01L27/1255 ,  H10B12/30

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US20230335180A1

公开(公告)日：2023-10-19

申请号：US18206117

申请日：2023-06-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

公开(公告)号：US20220345095A1

公开(公告)日：2022-10-27

申请号：US17619669

申请日：2020-06-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuichi YANAGISAWA ,  Shota MIZUKAMI ,  Kazuki TSUDA

IPC: H03F3/195 ,  H03F1/02 ,  H01L29/786

Abstract: A semiconductor device is provided in which power consumption is reduced and an increase in circuit area is inhibited. The semiconductor device includes a high frequency amplifier circuit, an envelope detection circuit, and a power supply circuit. The power supply circuit has a function of supplying a power supply potential to the high frequency amplifier circuit, an output of the high frequency amplifier circuit is connected to the envelope detection circuit, and an output of the envelope detection circuit is connected to the power supply circuit. The power supply circuit can reduce the power consumption by changing the power supply potential in accordance with the output of the high frequency amplifier circuit. The use of an OS transistor in the envelope detection circuit can inhibit an increase in circuit area.

公开(公告)号：US20220149044A1

公开(公告)日：2022-05-12

申请号：US17579640

申请日：2022-01-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/06 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

公开(公告)号：US20210183860A1

公开(公告)日：2021-06-17

申请号：US17047143

申请日：2019-04-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Takanori MATSUZAKI

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A novel semiconductor device is provided. A semiconductor device includes a plurality of cell arrays and a plurality of peripheral circuits. The cell array includes a plurality of memory cells. The peripheral circuit includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit. The first driver circuit and the second driver circuit each have a function of supplying a selection signal to the cell array. The first amplifier circuit and the second amplifier circuit each have a function of amplifying a potential input from the cell array. The third amplifier circuit and the fourth amplifier circuit each have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit. The first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit have a region overlapping with the cell array. A transistor included in the memory cell includes a metal oxide in a channel formation region.