公开(公告)号：US20150346791A1

公开(公告)日：2015-12-03

申请号：US14290779

申请日：2014-05-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Anh Ly ,  Hung Quoc Nguyen

IPC: G06F1/26 ,  G06F1/28

CPC classification number: G06F1/266 ,  G06F1/28 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/4074 ,  G11C16/30 ,  H03K19/018521

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed.

Abstract translation: 公开了一种用于改进嵌入式闪存设备内的电源排序的系统和方法。

公开(公告)号：US20150325300A1

公开(公告)日：2015-11-12

申请号：US14275362

申请日：2014-05-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Anh Ly ,  Victor Markov

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/3427

Abstract: An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.

Abstract translation: 公开了一种改进的控制门解码设计，用于在闪速存储器单元的编程期间减少干扰。 在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。

公开(公告)号：US08867281B2

公开(公告)日：2014-10-21

申请号：US13958410

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/00 ,  H02M3/156 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/06 ,  G11C5/145 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H02M3/073

Abstract: A hybrid charge pump and control circuit for use in a memory device is disclosed.

Abstract translation: 公开了一种用于存储器件的混合电荷泵和控制电路。

公开(公告)号：US08836411B2

公开(公告)日：2014-09-16

申请号：US13726522

申请日：2012-12-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

IPC: G05F1/62 ,  H02M3/18 ,  G05F3/02 ,  H02M3/07 ,  H02M1/32

CPC classification number: G05F3/02 ,  H02M3/073 ,  H02M2001/322

Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

Abstract translation: 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。

公开(公告)号：US12237011B2

公开(公告)日：2025-02-25

申请号：US17853315

申请日：2022-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

公开(公告)号：US20240256846A1

公开(公告)日：2024-08-01

申请号：US18135664

申请日：2023-04-17

Applicant: Silicon Storage Technology, Inc

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G06N3/065

CPC classification number: G06N3/065

Abstract: Numerous examples are disclosed of multiplexors coupled to rows in a neural network array. In one example, a system comprises a neural network array of non-volatile memory cells comprising i rows, where i is a multiple of 2; j row registers, where j

公开(公告)号：US11915747B2

公开(公告)日：2024-02-27

申请号：US17856839

申请日：2022-07-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N3/065

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

公开(公告)号：US11727989B2

公开(公告)日：2023-08-15

申请号：US17734807

申请日：2022-05-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L29/788 ,  H10B41/30 ,  G06N3/045

CPC classification number: G11C16/0425 ,  G06N3/08 ,  H01L29/7883 ,  H01L29/7885 ,  H10B41/30 ,  G06N3/045

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.

公开(公告)号：US20230178147A1

公开(公告)日：2023-06-08

申请号：US18103383

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  G06N3/065

CPC classification number: G11C11/54 ,  G11C16/0425 ,  G06N3/063 ,  G11C16/26 ,  G11C16/0416 ,  G11C16/28 ,  H03F3/005 ,  H03M1/164 ,  G06N3/065 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

公开(公告)号：US20230141943A1

公开(公告)日：2023-05-11

申请号：US17585261

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Kha Nguyen ,  Hien Pham ,  Duc Nguyen

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/30 ,  G11C16/26

Abstract: Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed. In one embodiment, a transceiver comprises a PMOS transistor and a native NMOS transistor. In another embodiment, a transceiver comprises a PMOS transistor, an NMOS transistor, and a native NMOS transistor.