公开(公告)号：US11978802B2

公开(公告)日：2024-05-07

申请号：US16218493

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/76832 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

公开(公告)号：US20240105719A1

公开(公告)日：2024-03-28

申请号：US18524934

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US20240096895A1

公开(公告)日：2024-03-21

申请号：US18522687

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien Huang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Shi Ning Ju ,  Guan-Lin Chen

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7851

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

公开(公告)号：US20240088145A1

公开(公告)日：2024-03-14

申请号：US18519263

申请日：2023-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Chih-Hao Wang ,  Kuo-Cheng Ching

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

公开(公告)号：US11855216B2

公开(公告)日：2023-12-26

申请号：US17869163

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Pei-Hsun Wang ,  Lo-Heng Chang ,  Jung-Hung Chang

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

公开(公告)号：US20230387264A1

公开(公告)日：2023-11-30

申请号：US18365315

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/66795 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/785 ,  H01L27/0924 ,  H01L21/823814

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US20230369456A1

公开(公告)日：2023-11-16

申请号：US18181678

申请日：2023-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Chih-Hao Wang ,  Chien Ning Yao ,  Tsung-Han Chuang ,  Kuo-Cheng Chiang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/41733 ,  H01L21/823431 ,  H01L21/823412 ,  H01L21/823418

Abstract: A semiconductor device with back-side contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a stack of nanostructured semiconductor layers disposed adjacent to the first S/D region, a gate structure surrounding each of the nanostructured semiconductor layers, a first pair of spacers disposed on opposite sidewalls of the first S/D region, a second pair of spacers disposed on opposite sidewalls of the second S/D region, a third pair of spacers disposed on opposite sidewalls of the gate structure, a first contact structure disposed on a first surface of the first S/D region, and a second contact structure disposed on a second surface of the first S/D region. The first and second surfaces are opposite to each other. The first pair of spacers are disposed on opposite sidewalls of the second contact structure.

公开(公告)号：US11791401B2

公开(公告)日：2023-10-17

申请号：US16947381

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: A method of fabricating a device includes providing a fin having a plurality of channel layers and a plurality of multilayer epitaxial layers interposing the plurality of channel layers. The multilayer epitaxial layers include a first epitaxial layer interposed between second and third epitaxial layers. The first epitaxial layer has a first etch rate and the second and third epitaxial layers have a second etch rate greater than the first etch rate. The method further includes laterally etching the first, second, and third epitaxial layers to provide a convex sidewall profile on opposing lateral surfaces of the multilayer epitaxial layers. The method further includes forming an inner spacer between adjacent channel layers. The inner spacer interfaces the convex sidewall profile of the multilayer epitaxial layers along a first inner spacer sidewall surface. The method further includes replacing the multilayer epitaxial layers with a portion of a gate structure.

公开(公告)号：US11676819B2

公开(公告)日：2023-06-13

申请号：US17809847

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L27/092 ,  H01L29/786 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L21/28123 ,  H01L21/31055 ,  H01L21/32136 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

公开(公告)号：US20230034360A1

公开(公告)日：2023-02-02

申请号：US17671737

申请日：2022-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Lo-Heng Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Lin-Yu Huang

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.