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    Semiconductor integrated circuit
    101.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06278628B1

    公开(公告)日：2001-08-21

    申请号：US09532734

    申请日：2000-03-22

    申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

    发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Kazuhiko Kajigaya ,  Katsutaka Kimura ,  Tsugio Takahashi

    IPC分类号： G11C506

    CPC分类号： G11C7/02 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882

    摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. A data line-word line imbalance generates large noise when the data lines are subjected to amplification, which is highly likely to invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

    摘要翻译： 在追求微型制造的大规模集成DRAM中，数据线字线耦合电容在配对数据线之间不平衡。 当数据线被放大时，数据线字线不平衡产生大的噪声，这很可能引起数据线上的非常小的信号的恶化和数据的错误放大。 连接到连接到一个数据线的多个存储单元的多个字线中的一个或几个交替地连接到布置在存储器阵列的相对侧上的子字驱动器阵列。 当数据线被放大时，正和负字线噪声分量在子字驱动器中彼此抵消，从而可以减小字线噪声。 因此，可以防止由读出放大器读出的信号劣化，从而提高存储器操作的可靠性。

    SEMICONDUCTOR DEVICE
    102.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20120092921A1

    公开(公告)日：2012-04-19

    申请号：US13330362

    申请日：2011-12-19

    申请人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C7/18 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.

    摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关来并行提供两个电流路径。

    Timing control circuit and semiconductor storage device
    104.
    发明授权
    Timing control circuit and semiconductor storage device 有权
    定时控制电路和半导体存储设备

    公开(公告)号：US07973582B2

    公开(公告)日：2011-07-05

    申请号：US12205668

    申请日：2008-09-05

    申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    IPC分类号： H03H11/26

    CPC分类号： H03K5/15033

    摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

    摘要翻译： 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m·T1 + n·（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m·T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n·（T2 / L）的精细定时信号。 m和n的值可以由寄存器设置。

    Semiconductor device
    105.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07903492B2

    公开(公告)日：2011-03-08

    申请号：US12314860

    申请日：2008-12-17

    申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

    摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).

    摘要翻译： 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

    Semiconductor integrated circuit device
    106.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07848177B2

    公开(公告)日：2010-12-07

    申请号：US12269098

    申请日：2008-11-12

    申请人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Shinya Kajiyama ,  Yutaka Shinagawa ,  Makoto Mizuno ,  Hideo Kasai ,  Takao Watanabe ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1039 ,  G11C7/1075 ,  G11C16/26

    摘要： The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.

    摘要翻译： 半导体集成电路装置包括：第一锁存器，其可以保持X解码器的输出信号，并且在X解码器之后的后级中将信号传送到字驱动器; 第二锁存器，其可以保持Y解码器的输出信号，并且在Y解码器之后的后级中将信号传送到列多路复用器; 以及第三锁存器，其可以保持读出放大器的输出信号，并且在读出放大器之后的后级中将该信号传送到输出缓冲器。 该结构使得可以对一系列用于读取存储在非易失性半导体存储器中的数据的处理进行管线控制，并且即使在来自CPU的访问请求冲突的情况下也能够进行低延迟访问。

    Semiconductor memory device
    107.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07835171B2

    公开(公告)日：2010-11-16

    申请号：US12172198

    申请日：2008-07-11

    申请人： Kazuo Ono ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo Ono ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0064 ,  G11C13/0011 ,  G11C13/0069 ,  G11C16/3468 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2213/52 ,  G11C2213/79

    摘要： A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.

    摘要翻译： 电阻变化存储器减少了编程之后的电阻值的不均匀性，使得可以以高速度对存储器单元执行重写操作。 参考电阻与电阻变化存储单元串联连接，传感器放大器检测存储单元和参考电阻之间的中间节点处的电位是否超过给定阈值电压，以便基于 检测结果。

    SEMICONDUCTOR DEVICE
    108.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090273961A1

    公开(公告)日：2009-11-05

    申请号：US12430067

    申请日：2009-04-25

    申请人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    发明人： Kazuo ONO ,  Riichiro Takemura ,  Tomonori Sekiguchi

    IPC分类号： G11C5/02 ,  G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/0023 ,  G11C7/18 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.

    摘要翻译： 在电阻改变存储器中提供一种用于在不增加电源电压的情况下增加重写电流并且还减少在重写之后的电阻状态的存储器阵列内的位置依赖性的技术，其中存储器单元的电阻值在逻辑值“1 “和”0“。 在电阻变化存储器中，将位线形成为分层结构，在本地位线的两端设置用于连接到全局位线的位线选择开关，并且位线选择开关的控制方式发生变化 在写入和读取中，从而实现它们中的每一个的最佳阵列配置。 更具体地，在写入和读取中，通过同时接通位线选择开关并联提供两个电流路径。

    Semiconductor device having a sense amplifier array with adjacent ECC
    110.
    发明授权
    Semiconductor device having a sense amplifier array with adjacent ECC 有权
    具有具有相邻ECC的读出放大器阵列的半导体器件

    公开(公告)号：US07603592B2

    公开(公告)日：2009-10-13

    申请号：US11495550

    申请日：2006-07-31

    申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

    发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1044 ,  G11C2029/0409

    摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.

    摘要翻译： 提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。 将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。 除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。 通过这种方式，可以更换制造过程中发生的错误。 此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。