公开(公告)号：US10566300B2

公开(公告)日：2020-02-18

申请号：US15876734

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Scott Pozder ,  Thiagarajan Raman ,  Kristina Young-Fisher ,  David Stone

IPC: H01L29/00 ,  H01L23/00

Abstract: Bond pad structures and methods for fabricating bond pad structures. A bond pad and a plurality of fill lines are formed on the top surface of a dielectric layer. The fill lines are arranged on the top surface of the dielectric layer adjacent to the bond pad, and may be separated from the bond pad by a fill keep-out zone. One or more Under Bump Metallurgy (UBM) layers may be arranged on the bond pad and may extend outwardly to overlap with the fill lines.

公开(公告)号：US10566201B1

公开(公告)日：2020-02-18

申请号：US16174510

申请日：2018-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hui Zang ,  Laertis Economikos ,  Andre LaBonte

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/423 ,  H01L23/535 ,  H01L29/66

Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.

公开(公告)号：US10564554B2

公开(公告)日：2020-02-18

申请号：US15874039

申请日：2018-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Liang Cao ,  Jed H. Rankin ,  Jie Zhang ,  Yulu Chen

IPC: G03F7/20 ,  G06F17/50 ,  G03F1/42 ,  G03F7/26 ,  G03F9/00 ,  G03F1/36 ,  G03F1/84 ,  G03F1/70 ,  H01L21/027 ,  H01L21/66

Abstract: Embodiments of a method include: converting at least one image of a printed mask to a plurality of representative contours, each corresponding to mask patterns in the printed mask; determining whether the printed mask includes a printing defect based on whether the plurality of representative contours violates a set of contour tolerances for the printed mask; in response to at least one of plurality of representative contours violating at least one of the set of contour tolerances: identifying a location where a representative contour violates the at least one of the set of contour tolerances, and generating an instruction to adjust a layout for the printed mask, based on the violating of the at least one of the set of contour tolerances; and in response to none of the plurality of representative contours violating the set of contour tolerances, flagging a layout for the printed mask as compliant.

公开(公告)号：US20200051923A1

公开(公告)日：2020-02-13

申请号：US16654354

申请日：2019-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cung D. Tran ,  Huaxiang Li ,  Bradley Morgenfeld ,  Xintuo Dai ,  Sanggil Bae ,  Rui Chen ,  Md Motasim Bellah ,  Dongyue Yang ,  Minghao Tang ,  Christian J. Ayala ,  Ravi Prakash Srivastava ,  Kripa Nidhan Chauhan ,  Pavan Kumar Chinthamanipeta Sripadarao

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/027 ,  G03F7/16

Abstract: In an exemplary method, a first layer is formed on a substrate. First overlay marks are formed in a first zone of the first layer. A non-transparent layer is formed on top of the first layer. At least a portion of the non-transparent layer is removed from an area above the first zone of the first layer. This provides optical access to the first overlay marks. A second layer is formed on top of the non-transparent layer. Second overlay marks are formed in a second zone of the second layer. Position information is obtained from each of the first overlay marks and the second overlay marks.

公开(公告)号：US10559503B2

公开(公告)日：2020-02-11

申请号：US15728445

申请日：2017-10-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/027 ,  H01L27/092 ,  G06F17/50 ,  H01L21/768 ,  H01L27/088

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US20200044069A1

公开(公告)日：2020-02-06

申请号：US16049849

申请日：2018-07-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Andreas Knorr ,  Srikanth Balaji Samavedam

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/762

Abstract: Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods.

公开(公告)号：US10553486B1

公开(公告)日：2020-02-04

申请号：US16047037

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/321

Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

公开(公告)号：US20200035555A1

公开(公告)日：2020-01-30

申请号：US16047037

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45

Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

公开(公告)号：US10546943B2

公开(公告)日：2020-01-28

申请号：US15960965

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Arkadiusz Malinowski ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/265 ,  H01L21/3065

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

公开(公告)号：US10546853B2

公开(公告)日：2020-01-28

申请号：US16016058

申请日：2018-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/51 ,  H01L49/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/66

Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.