公开(公告)号：US20060094180A1

公开(公告)日：2006-05-04

申请号：US10980522

申请日：2004-11-02

Applicant: Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

Inventor： Mark Doczy ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Suman Datta ,  Robert Chau

IPC: H01L21/8238

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, forming a barrier layer on the high-k gate dielectric layer, and forming a fully silicided gate electrode on the barrier layer.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成高k栅极电介质层，在高k栅极电介质层上形成阻挡层，并在阻挡层上形成完全硅化的栅电极。

公开(公告)号：US20060091467A1

公开(公告)日：2006-05-04

申请号：US10977261

申请日：2004-10-29

Applicant: Brian Doyle ,  Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Amlan Majumdar ,  Marko Radosavljevic ,  Robert Chan

Inventor： Brian Doyle ,  Suman Datta ,  Justin Brask ,  Jack Kavalieros ,  Amlan Majumdar ,  Marko Radosavljevic ,  Robert Chan

IPC: H01L29/94

CPC classification number: H01L29/0847 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/76 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834

Abstract: An embodiment of the present invention is a technique to fabricate a semiconductor device having low off state leakage current. A gate structure of a first device is formed on a substrate layer having a hardmask. A channel is formed underneath the gate structure having a width to support the gate structure. An oxide or a dielectric layer is deposited on the substrate layer. A doped polysilicon layer is deposited on the oxide layer. A recessed junction area is formed on the doped polysilicon layer between the first device and an adjacent device.

Abstract translation: 本发明的实施例是制造具有低截止状态的漏电流的半导体器件的技术。 第一器件的栅极结构形成在具有硬掩模的衬底层上。 在具有宽度的栅极结构下方形成沟道以支撑栅极结构。 氧化物或电介质层沉积在衬底层上。 掺杂的多晶硅层沉积在氧化物层上。 在第一器件和相邻器件之间的掺杂多晶硅层上形成凹入的接合区域。

公开(公告)号：US20060051882A1

公开(公告)日：2006-03-09

申请号：US11210220

申请日：2005-08-22

Applicant: Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

Inventor： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC: H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US07005366B2

公开(公告)日：2006-02-28

申请号：US10923472

申请日：2004-08-20

Applicant: Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

Inventor： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

公开(公告)号：US20050237850A1

公开(公告)日：2005-10-27

申请号：US11165724

申请日：2005-06-24

Applicant: Suman Datta ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott Hareland

Inventor： Suman Datta ,  Brian Doyle ,  Robert Chau ,  Jack Kavalieros ,  Bo Zheng ,  Scott Hareland

IPC: G11C11/412 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786 ,  G11C8/02

CPC classification number: G11C11/412 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

公开(公告)号：US06914295B2

公开(公告)日：2005-07-05

申请号：US10887609

申请日：2004-07-08

Applicant: Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

Inventor： Robert S. Chau ,  Brian S. Doyle ,  Jack Kavalieros ,  Douglas Barlage ,  Suman Datta ,  Scott A. Hareland

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/772 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0554 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

公开(公告)号：US20050139928A1

公开(公告)日：2005-06-30

申请号：US10748383

申请日：2003-12-29

Applicant: Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Scott Hareland ,  Matthew Metz ,  Chris Barns ,  Robert Chau

Inventor： Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Scott Hareland ,  Matthew Metz ,  Chris Barns ,  Robert Chau

IPC: H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后 用n型金属栅极材料填充凹部。

公开(公告)号：US06893927B1

公开(公告)日：2005-05-17

申请号：US10805880

申请日：2004-03-22

Applicant: Uday Shah ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Uday Shah ,  Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/513 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for making a semiconductor device is described. In that method, a metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the sides of the masking layer are lined with a sacrificial layer.

Abstract translation: 描述制造半导体器件的方法。 在该方法中，在形成在基板上的电介质层上形成金属层。 在金属层上形成掩模层之后，掩模层的侧面衬有牺牲层。

公开(公告)号：US06808993B2

公开(公告)日：2004-10-26

申请号：US10339783

申请日：2003-01-08

Applicant: Christine M. Finnie ,  Pauline N. Jacob ,  Nick Lindert ,  Keith M. Jackson ,  Kirk Althoff ,  Jack Hwang ,  Jack Kavalieros ,  James R. Mueller

Inventor： Christine M. Finnie ,  Pauline N. Jacob ,  Nick Lindert ,  Keith M. Jackson ,  Kirk Althoff ,  Jack Hwang ,  Jack Kavalieros ,  James R. Mueller

IPC: H01L21336

CPC classification number: H01L21/28202 ,  H01L21/28185 ,  H01L21/3144 ,  H01L21/3185 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

Abstract: An in-situ ultra dilute ammonia nitridation process and apparatus of the following ultra-thin chemically tailored gate dielectrics: DCE/O2 (Trans 1,2-Dichloroethylene) based ultra-thin gate dielectric; Nitric Oxide (NO) based ultra-thin gate dielectric that has been re-oxidized via a DCE/O2 (Trans 1,2-Dichloroethylene) process; “dry-wet” DCE (Trans 1,2-Dichloroethylene)/O2-H2O/O2) based ultra-thin gate dielectric; and ultra dilute, less than 1E-7 moles NH3/mm2, nitridation of an ultra-thin gate dielectric. A vertical diffusion furnace (VDF) is provided to process the same. The ultra-thin chemically tailored gate dielectrics generated in a VDF with ultra-dilute NH3, below 1E-7 moles NH3/mm2, in-situ nitridation show a performance comparable or better to traditional ex-situ rapid thermal anneal (RTA) processing techniques for 90 nm CMOS technology. These methods replace and remove at least one process layer in the fabrication of CMOS devices using traditional ex-situ RTA processing, decreasing production costs, and improving fabrication cycle time, with equivalent or improved transistor performance.

Abstract translation: 一种原位超稀氨氮工艺及以下超薄化学定制栅极电介质的设备：DCE / O2（Trans 1,2--Dichloroethylene））超薄栅极电介质; 已经通过DCE / O2（反式1,2-二氯乙烯）方法再氧化的一氧化氮（NO）基超薄栅极电介质; “干湿”DCE（反式1,2-二氯乙烯）/ O 2 -H 2 O / O 2）基超薄栅极电介质; 并且超稀释，小于1E-7摩尔NH 3 / mm 2，氮化超薄栅极电介质。 提供垂直扩散炉（VDF）来处理它。 在具有超稀释NH 3，低于1E-7摩尔NH 3 / mm 2的VDF中产生的超薄化学定制的栅极电介质在现场氮化显示出与传统的非原位快速热退火（RTA）相当或更好的性能 ）90nm CMOS技术的处理技术。 这些方法在使用传统的异地RTA处理，降低生产成本和改进制造周期时间的CMOS器件制造中至少替代和去除至少一个工艺层，具有等效或改进的晶体管性能。

公开(公告)号：US09397166B2

公开(公告)日：2016-07-19

申请号：US13977394

申请日：2011-12-20

Applicant: Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

Inventor： Van H. Le ,  Harold W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack Kavalieros ,  Niloy Mukherjee

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y99/00

CPC classification number: H01L29/7848 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762

Abstract: Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.

Abstract translation: 本发明的实施例提供具有应变通道区域的晶体管结构。 通过源极和漏极区域中相对于晶体管的沟道区域的晶格失配产生应变。 在本发明的实施例中，晶体管沟道区由锗，硅，锗和硅的组合，或锗，硅和锡的组合组成，源极和漏极区由掺杂的III-V族化合物半导体 材料。 本发明的实施例可用于各种晶体管结构，例如具有由纳米线或纳米带构成的沟道区的触发，大电流和单栅极晶体管和晶体管。