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    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
    111.
    发明申请
    CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
    记忆系统中的时钟模式确定

    公开(公告)号：US20140133243A1

    公开(公告)日：2014-05-15

    申请号：US14158215

    申请日：2014-01-17

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： Peter B. GILLINGHAM ,  Graham ALLAN

    IPC: G11C16/10

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/14

    Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

    Abstract translation: 描述了用于存储器件的时钟模式配置电路。 存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。 可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。 每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从先前存储器件接收源同步时钟信号的串行模式。 根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。 通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

    FLASH MEMORY CONTROLLER HAVING MULTI MODE PIN-OUT
    112.
    发明申请
    FLASH MEMORY CONTROLLER HAVING MULTI MODE PIN-OUT 审中-公开
    具有多模式引脚输出的闪存控制器

    公开(公告)号：US20140122777A1

    公开(公告)日：2014-05-01

    申请号：US13836113

    申请日：2013-03-15

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： HakJune OH ,  Jin-Ki KIM ,  Young Goan KIM ,  Hyun Woong LEE

    IPC: G06F3/06

    CPC classification number: G06F3/0661 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/1694

    Abstract: A memory controller of a data storage device which communicates with a host, has channel control modules each being configurable to have at three different pinout assignments for interfacing with two different types of memory devices operating with different memory interface protocols. One pinout assignment corresponds to a memory interface protocol where memory devices can be connected in parallel with each other. Two other pinout assignments correspond respectively to inbound and outbound signals of another memory interface protocol where memory devices are serially connected with each other. In this mode of operation, one channel control module is configured to provide the outbound signals while another channel control module is configured to receive the inbound signals. Each memory port of the channel control modules includes port buffer circuitry configurable for different functional signal assignments. The configuration of each channel control module is selectable by setting predetermined ports or registers.

    Abstract translation: 与主机通信的数据存储设备的存储器控​​制器具有通道控制模块，每个通道控制模块可配置为具有三种不同的引脚分配，用于与使用不同存储器接口协议操作的两种不同类型的存储器件进行接口。 一个引脚分配对应于存储器设备可以彼此并联连接的存储器接口协议。 另外两个引脚分配分别对应于另一存储器接口协议的入站和出站信号，其中存储器设备彼此串联连接。 在这种操作模式中，一个信道控制模块被配置为提供出站信号，而另一个信道控制模块被配置为接收入站信号。 信道控制模块的每个存储器端口包括可配置用于不同功能信号分配的端口缓冲器电路。 每个通道控制模块的配置可以通过设置预定的端口或寄存器来选择。

    Flash multi-level threshold distribution scheme
    114.
    发明授权
    Flash multi-level threshold distribution scheme 有权
    闪存多级阈值分配方案

    公开(公告)号：US08711621B2

    公开(公告)日：2014-04-29

    申请号：US13892743

    申请日：2013-05-13

    Applicant: MOSAID Technologies Incorporated

    Inventor： Jin-Ki Kim

    IPC: G11C11/34

    CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

    Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

    Abstract translation: 用于多电平闪存单元的阈值电压分配方案，其中擦除阈值电压和至少一个编程的阈值电压位于擦除电压域中。 在擦除电压域中至少有一个编程的阈值电压降低了Vread电压电平，以最小化读取干扰效应，同时随着编程状态之间的阈值电压距离最大化，延长多电平闪存单元的使用寿命。 编程电压域大于0V时，擦除电压域可以小于0V。 因此，用于程序验证和读取具有在擦除电压域中的编程阈值电压和编程电压域的多电平闪存单元的电路使用负和正高电压。

    RING-OF-CLUSTERS NETWORK TOPOLOGIES
    116.
    发明申请
    RING-OF-CLUSTERS NETWORK TOPOLOGIES 有权
    环网络网络拓扑

    公开(公告)号：US20140115190A1

    公开(公告)日：2014-04-24

    申请号：US14057102

    申请日：2013-10-18

    Applicant: MOSAID Technologies Incorporated

    Inventor： Steven PRZYBYLSKI

    IPC: H04L12/46 ,  H04L12/42

    CPC classification number: H04L12/4637 ,  G06F13/4243 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H04L12/42 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/32225 ,  H01L2924/00012

    Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.

    Abstract translation: 在集群中的网络拓扑结构中，并行访问从属设备组，使得环周围的延迟与集群的数量成比例，与集成电路的数量成正比。 集群的设备共享输入和输出环段，使得到达输入段的数据包被集群中的所有设备接收和解释。 在其他实施例中，每个群集中的一个或全部除了一个从设备是睡着的或者被禁用的，使得它们不输入和解释传入的分组。 无论如何，在所有实施例中，集群的从站可能在控制器的方向下协作，以确保其中至少一个在任何给定时间主动地驱动输出段。 可以通过设备ID，集群ID或其组合来寻址设备。 本发明的实施例适用于利用多芯片模块实现和垂直电路堆叠的形式。

    FLASH MEMORY CONTROLLER HAVING DUAL MODE PIN-OUT
    117.
    发明申请
    FLASH MEMORY CONTROLLER HAVING DUAL MODE PIN-OUT 有权
    具有双模式引脚的闪存控制器

    公开(公告)号：US20140082260A1

    公开(公告)日：2014-03-20

    申请号：US13835968

    申请日：2013-03-15

    Applicant: MOSAID TECHNOLOGIES INCORPORATED

    Inventor： HakJune OH ,  Jin-Ki KIM ,  Young Goan KIM ,  Hyun Woong LEE

    IPC: G06F12/02

    CPC classification number: G06F12/0246 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/385

    Abstract: A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.

    Abstract translation: 与主机进行通信的数据存储设备的存储器控​​制器可配置为具有用于与相应不同类型的存储器件接口的至少两个不同的引脚分配。 每个引脚分配对应于特定的存储器接口协议。 存储器控制器的每个存储器接口端口基于所使用的选择的存储器接口协议，包括可配置用于不同功能信号分配的端口缓冲器电路。 通过设置存储器控制器的预定端口或寄存器来选择每个存储器接口端口的接口电路配置。

    LOCAL AREA NETWORK FOR DISTRIBUTING DATA COMMUNICATION, SENSING AND CONTROL SIGNALS
    118.
    发明申请
    LOCAL AREA NETWORK FOR DISTRIBUTING DATA COMMUNICATION, SENSING AND CONTROL SIGNALS 审中-公开
    用于分布数据通信，传感和控制信号的本地区网络

    公开(公告)号：US20140050228A1

    公开(公告)日：2014-02-20

    申请号：US14064442

    申请日：2013-10-28

    Applicant: MOSAID Technologies Incorporated

    Inventor： Yehuda Binder

    IPC: H04L12/24 ,  H04L12/931

    CPC classification number: H04L41/0836 ,  G05B2219/21039 ,  G05B2219/25181 ,  H04L12/40 ,  H04L12/40019 ,  H04L12/403 ,  H04L12/42 ,  H04L12/66 ,  H04L49/40

    Abstract: A network for carrying out control, sensing and data communications, composed of a plurality of nodes. Each node may be connected to a payload, which includes sensors, actuators and DTE's. The network is formed using a plurality of independent communication links, each based on electrically-conducting communication media composed of at least two conductors and interconnecting two nodes, in a point-to-point configuration. During network operation, nodes can be dynamically configured as either data-generating nodes, wherein data is generated and transmitted into the network, or as receiver/repeater/router nodes, wherein received data is repeated from a receiver port to all output ports.

    Abstract translation: 用于执行由多个节点组成的控制，感测和数据通信的网络。 每个节点可以连接到有效载荷，其中包括传感器，执行器和DTE。 网络使用多个独立的通信链路形成，每个通信链路基于由至少两个导体组成的导电通信介质并且以点对点配置互连两个节点。 在网络操作期间，节点可以被动态地配置为数据生成节点，其中数据被生成并发送到网络，或者作为接收器/中继器/路由器节点，其中接收的数据从接收器端口重复到所有的输出端口。

    High bandwidth memory interface
    119.
    发明授权
    High bandwidth memory interface 有权
    高带宽存储器接口

    公开(公告)号：US08654573B2

    公开(公告)日：2014-02-18

    申请号：US13743794

    申请日：2013-01-17

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. Gillingham ,  Bruce Millar

    IPC: G11C11/00

    CPC classification number: G11C5/06 ,  G06F1/12 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G11C8/18 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals. The buffer is configured to regenerate signals received on the bus lines for receipt by the synchronous memory devices, and to regenerate signals received from any one of the synchronous memory devices for receipt by the bus lines. The memory module may further include command lines and a clock line for providing commands and a clock signal to the synchronous memory devices via a command buffer. The combined data bus width of the memory module may be greater than the data bus width of any single one of synchronous memory device, and the total address space provided by the memory module may be larger than the data space for any single synchronous memory device.

    Abstract translation: 一种包括缓冲器和多个同步存储器件的存储器模块。 存储器模块还包括双向总线，并且每个同步存储器件具有双向数据终端。 缓冲器被配置为重新生成在总线上接收的信号以供同步存储器件接收，并且重新产生从任何一个同步存储器装置接收的信号，以便由总线接收。 存储器模块还可以包括命令行和用于经由命令缓冲器向同步存储器件提供命令和时钟信号的时钟线。 存储器模块的组合数据总线宽度可以大于同步存储器件中任何一个的数据总线宽度，并且由存储器模块提供的总地址空间可能大于任何单个同步存储器件的数据空间。

    SIMULTANEOUS READ AND WRITE DATA TRANSFER
    120.
    发明申请
    SIMULTANEOUS READ AND WRITE DATA TRANSFER 有权
    同时读取和写入数据传输

    公开(公告)号：US20140013041A1

    公开(公告)日：2014-01-09

    申请号：US13962062

    申请日：2013-08-08

    Applicant: Mosaid Technologies Incorporated

    Inventor： Peter B. GILLINGHAM

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0688 ,  G06F13/4243

    Abstract: A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.

    Abstract translation: 用于布置存储器件的控制器可以发出写入命令而不等待先前发出的读取命令的接收。 寻址的存储器件可以根据读取命令将数据读出到数据总线上，同时根据读取命令之后接收的写入命令写入数据。

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