公开(公告)号：US20160343729A1

公开(公告)日：2016-11-24

申请号：US15142365

申请日：2016-04-29

Applicant: Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

Inventor： Hyun-Jin SHIN ,  Hong-Suk KIM ,  Jung-Hwan KIM ,  Sang-Hoon LEE ,  Hun-Hyeong LIM ,  Yong-Seok CHO ,  Young-Dae KIM ,  Han-Vit YANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/0206 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成结构，所述结构包括金属图案，所述金属图案的至少一部分被暴露; 形成预备的缓冲氧化物层以覆盖该结构，金属氧化物层形成在金属图案的暴露部分; 并且使金属氧化物层脱氧，使得预备缓冲氧化物层转变成缓冲氧化物层。

公开(公告)号：US20160133643A1

公开(公告)日：2016-05-12

申请号：US14995586

申请日：2016-01-14

Applicant: Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

Inventor： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

Abstract translation: 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US20160098812A1

公开(公告)日：2016-04-07

申请号：US14845558

申请日：2015-09-04

Applicant: SANG CHUL YOON ,  SEONG WOON KIM ,  SANG HOON LEE

Inventor： SANG CHUL YOON ,  SEONG WOON KIM ,  SANG HOON LEE

IPC: G06T1/20 ,  G06T3/40 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T3/4092

Abstract: An application processor includes a first scaler including a first vertical scaler and a first horizontal scaler, and a second scaler including a second vertical scaler and a second horizontal scaler, wherein the second vertical scaler is selectively shared between the first scaler and the second scaler in response to a determination of resolution for an image being processed.

Abstract translation: 应用处理器包括包括第一垂直缩放器和第一水平缩放器的第一缩放器和包括第二垂直缩放器和第二水平缩放器的第二缩放器，其中在第一缩放器和第二缩放器之间选择性地共享第二垂直缩放器， 响应于正在处理的图像的分辨率的确定。

公开(公告)号：US09125276B2

公开(公告)日：2015-09-01

申请号：US12847379

申请日：2010-07-30

Applicant: Sang-hoon Lee

Inventor： Sang-hoon Lee

IPC: G09G3/36 ,  H05B33/08 ,  G09G3/34

CPC classification number: H05B33/086 ,  G09G3/3406 ,  G09G2310/0237 ,  G09G2310/08 ,  G09G2320/0238 ,  G09G2320/0633 ,  G09G2320/064 ,  G09G2330/021 ,  G09G2360/16

Abstract: A backlight unit and a display apparatus are provided. The display apparatus includes a driving unit which applies a driving current using a duty cycle controlling to the light emitting unit; and a controller which controls a first driving current to be applied to the light emitting unit in a section of a plurality of frame sections, and a second driving current to be applied to the light emitting unit in another section of the plurality of frame sections. Therefore, luminance representation of backlight in a low grayscale region can be improved.

Abstract translation: 提供背光单元和显示装置。 显示装置包括驱动单元，该驱动单元使用占空比控制将驱动电流施加到发光单元; 以及控制器，其控制在多个框架部分的一部分中施加到所述发光单元的第一驱动电流，以及施加到所述多个框架部分的另一部分中的所述发光单元的第二驱动电流。 因此，可以提高低灰度区域中的背光的亮度表示。

公开(公告)号：US20150220269A1

公开(公告)日：2015-08-06

申请号：US14610513

申请日：2015-01-30

Applicant: Sang Hoon LEE ,  Dong-Woo KIM

Inventor： Sang Hoon LEE ,  Dong-Woo KIM

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7208 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: An operating method of a storage device includes receiving an operation request from a host. The method includes interpreting the operation request as one of a multi-plane operation request and a 1-plane operation request. The method includes outputting an operation sequence corresponding to the interpreted operation request. The storage device includes at least one vertical flash memory device and a memory controller to control the at least one vertical flash memory device.

Abstract translation: 存储装置的操作方法包括从主机接收操作请求。 该方法包括将操作请求解释为多平面操作请求和1平面操作请求之一。 该方法包括输出与解释的操作请求对应的操作序列。 存储设备包括至少一个垂直闪存设备和用于控制至少一个垂直闪存设备的存储器控​​制器。

公开(公告)号：US09099093B2

公开(公告)日：2015-08-04

申请号：US11984421

申请日：2007-11-16

Applicant: Chang-kyu Choi ,  Kwang-il Hwang ,  Sun-gi Hong ,  Young-hun Sung ,  Yeun-bae Kim ,  Yong Kim ,  Sang-hoon Lee ,  Hong Jeong

Inventor： Chang-kyu Choi ,  Kwang-il Hwang ,  Sun-gi Hong ,  Young-hun Sung ,  Yeun-bae Kim ,  Yong Kim ,  Sang-hoon Lee ,  Hong Jeong

IPC: G10L21/00 ,  G10L21/02 ,  G10L25/93 ,  G10L21/0208 ,  G10L21/0364 ,  G10L25/78 ,  G10L25/90

CPC classification number: G10L21/0208 ,  G10L21/0364 ,  G10L25/78 ,  G10L25/90

Abstract: The present invention relates to an apparatus and method of improving intelligibility of a voice signal. A method of improving intelligibility of a voice signal according to an embodiment of the present invention includes analyzing a background noise signal on a call receiving side, classifying a received voice signal into a silence signal, an unvoiced sound signal, and a voiced sound signal, and intensifying the classified unvoiced sound signal and voiced sound signal on the basis of the analyzed background noise signal on the call receiving side.

Abstract translation: 本发明涉及提高语音信号的可懂度的装置和方法。 根据本发明的实施例的提高语音信号的可懂度的方法包括分析呼叫接收侧的背景噪声信号，将接收的语音信号分类为静音信号，无声声音信号和浊音信号， 基于呼叫接收侧的分析背景噪声信号，加强分类的无声声音信号和浊音信号。

公开(公告)号：US20150160880A1

公开(公告)日：2015-06-11

申请号：US14454268

申请日：2014-08-07

Applicant: Soonbok JANG ,  Sungho SEO ,  Sang-Hoon LEE

Inventor： Soonbok JANG ,  Sungho SEO ,  Sang-Hoon LEE

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  Y02D10/154

Abstract: A memory card includes a first signal terminal configured to output a first signal; a second signal terminal configured to output a second signal, the first and second signals being complementary to each other; and a controller configured to drive the first and second signal terminals to have a negative state until a link connection is performed after power is supplied to the memory card. When a level of the first signal is greater than a level of the second signal, the first and second signal terminals are in a positive state, whereas when a level of the first signal is smaller than a level of the second signal, the first and second signal terminals are in the negative state.

Abstract translation: 存储卡包括被配置为输出第一信号的第一信号端子; 第二信号端子，被配置为输出第二信号，所述第一和第二信号彼此互补; 以及控制器，被配置为在向存储卡提供电力之后，驱动第一和第二信号端子具有负状态直到执行链接连接。 当第一信号的电平大于第二信号的电平时，第一和第二信号端子处于正状态，而当第一信号的电平小于第二信号的电平时，第一和第二信号 第二信号端子处于负状态。

公开(公告)号：US09001587B2

公开(公告)日：2015-04-07

申请号：US13618336

申请日：2012-09-14

Applicant: Hee-seok Eun ,  Sang-hoon Lee ,  Jae-hong Kim ,  Sun-mi Yoo ,  Seok-min Yoon ,  Jong-youl Lee

Inventor： Hee-seok Eun ,  Sang-hoon Lee ,  Jae-hong Kim ,  Sun-mi Yoo ,  Seok-min Yoon ,  Jong-youl Lee

IPC: G11C16/06 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

Abstract: A reading method of a flash memory, the reading method including: sensing hard data of a first target page by using a first hard read voltage; and generating soft data of the first target page by using at least one pair of, that is, two, first soft read voltages whose voltage levels are different from a voltage level of the first hard read voltage, while the flash memory performs a first operation on the hard data.

Abstract translation: 一种闪存的读取方法，所述读取方法包括：通过使用第一硬读取电压来感测第一目标页面的硬数据; 以及通过使用电压电平不同于第一硬读取电压的电压电平的至少一对，即两个第一软读取电压来产生第一目标页面的软数据，而闪存执行第一操作 对硬数据。

公开(公告)号：US08990535B2

公开(公告)日：2015-03-24

申请号：US13564076

申请日：2012-08-01

Applicant: Hyun Seok Kim ,  Sung Bin Kim ,  Sung-Hwan Bae ,  Jong-Nam Baek ,  Sang Hoon Lee

Inventor： Hyun Seok Kim ,  Sung Bin Kim ,  Sung-Hwan Bae ,  Jong-Nam Baek ,  Sang Hoon Lee

IPC: G06F12/00 ,  G06F13/16 ,  G06F11/00 ,  G06F11/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G06F13/16 ,  G06F11/00 ,  G06F11/1048 ,  G06F11/1076 ,  G11C16/26 ,  G11C16/349

Abstract: A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by using the first RTC value read from the non-volatile memory and a second RTC value indicating a time-of-day when a read operation is performed, when the read operation for the data programmed to the storage region is performed, and decreasing a maximum count of a read retry operation by using the information, when the read retry operation is performed for the storage region.

Abstract translation: 公开了一种用于操作能够控制读取重试操作的最大计数的存储器控​​制器的方法。 该方法包括编程第一实时时钟（RTC）值，其指示在将数据编程到非易失性存储器的存储区域的程序操作时执行程序操作的时间，获得用于存储的信息 通过使用从非易失性存储器读取的第一RTC值和表示执行读取操作的时间的第二RTC值，执行对存储区域的编程的数据的读取操作，并且减少 当对存储区域执行读取重试操作时，通过使用该信息的重试操作的最大计数。

公开(公告)号：US08970637B2

公开(公告)日：2015-03-03

申请号：US12591358

申请日：2009-11-17

Applicant: Sung Joon Moon ,  Sang Hoon Lee ,  Kyu Ha Oh

Inventor： Sung Joon Moon ,  Sang Hoon Lee ,  Kyu Ha Oh

IPC: G09G5/10 ,  G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3611 ,  G09G3/2055 ,  G09G2340/0435 ,  G09G2360/16

Abstract: A frame rate control method capable of enhancing picture-quality is disclosed. The frame rate control method generates red, green, and blue frame rate control signals by frame-rate-modulating red, green, and blue frame rate control patterns on the basis of lower-bit red, green, and blue data. The lower-bit red, green, and blue data are extracted from red, green, and blue data. The red, green and blue frame rate control patterns are obtained through a process of shifting basic frame rate control patterns by different sub-pixel numbers in one direction. The basic frame rate control patterns are established for a plurality of frames.

Abstract translation: 公开了一种能够提高图像质量的帧率控制方法。 帧速率控制方法基于较低位的红，绿和蓝数据，通过对红，绿和蓝帧速控制模式进行帧速率调制，生成红，绿，蓝帧速控制信号。 红色，绿色和蓝色数据中的低位红，绿和蓝数据从​​红色，绿色和蓝色数据中提取。 通过在一个方向上通过不同的子像素数移动基本帧速率控制模式的处理来获得红色，绿色和蓝色帧速率控制模式。 为多个帧建立基本的帧速率控制模式。