公开(公告)号：US09678530B2

公开(公告)日：2017-06-13

申请号：US14819444

申请日：2015-08-06

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Hung Chen

IPC: G06F17/50 ,  H03K19/177 ,  G06F1/10 ,  H01L23/522

CPC classification number: G06F1/10 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/62 ,  G06F2217/84 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/17736 ,  H03K19/1774 ,  H01L2924/00

Abstract: An clock skew adjusting structure is provided. The clock skew adjusting structure includes a substrate, a wiring structure, a first active component and a second active component. The wiring structure includes at least a wiring layer and at least a via, the via is configured for different wiring layers to be electrically connected with each other. The first active component is formed on the substrate and configured for delivering a clock signal to the wiring structure. The second active component is formed on the substrate and electrically connected to the first active component through the wiring structure thus forming a timing path. The second active component receives the clock signal through the timing path.

公开(公告)号：US20170047439A1

公开(公告)日：2017-02-16

申请号：US15156363

申请日：2016-05-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chun-Yu Chen ,  Chung-Ting Huang ,  Ming-Hua Chang ,  Tien-Chen CHAN ,  Yen-Hsing CHEN ,  Hsin-Chang WU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/16 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L21/26506 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).

Abstract translation: 本发明提供一种鳍状场效应晶体管（FinFET），包括：具有翅片结构的衬底; 在所述翅片结构上形成有在所述沟槽中生长的合金的多个沟槽; 所述翅片结构上的栅极结构垂直于所述鳍状结构在所述多个沟槽之间的延伸方向; 以及由所述栅极结构暴露并且设置在所述栅极结构和所述合金之间的所述鳍状结构的表面上的非晶层。 本发明还提供了一种鳍状场效应晶体管（FinFET）的制造方法。

公开(公告)号：US20160372476A1

公开(公告)日：2016-12-22

申请号：US14742589

申请日：2015-06-17

Applicant: United Microelectronics Corporation

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/11 ,  H01L21/768 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Abstract translation: 提供半导体器件和制造这种半导体器件的方法用于改进的FinFET存储器单元，以避免经常在位单元的金属触点之间发生电短路，其中餐触点位于相邻虚拟边缘单元的虚拟栅极旁边。 在一个实施例中，在衬底表面上的栅极层的图案化期间，使用改进的栅极槽图案来延伸与位线相邻的一个或多个栅极槽的长度，以便图形化和分割靠近金属的伪栅极线 活动存储单元的触点。 在另一个实施例中，在栅极线图案化期间，调整邻近有源存储器单元设置的一个或多个虚拟栅极线之间的距离，使得它们在虚设边缘单元内的位置移位以远离有源存储器的金属触点 细胞。

公开(公告)号：US09478457B2

公开(公告)日：2016-10-25

申请号：US14957585

申请日：2015-12-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Ming-Shing Chen ,  Yu-Ting Wang ,  Ming-Hui Chang

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76224

Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

Abstract translation: 半导体器件中的浅沟槽隔离结构及其制造方法。 该方法包括以下步骤。 衬底上设置衬垫氧化物层和其上的第一图案化的光刻胶层。 在对应于第一图案化光致抗蚀剂层的基板中形成第一沟槽。 第一介电层沉积在第一沟槽和衬底上。 提供第二图案化光致抗蚀剂层以在第一电介质层中形成开口，并且在衬底中形成对应于第二图案化光致抗蚀剂层的第二沟槽。 沉积第二电介质层以覆盖衬底中的第一沟槽和第二沟槽以及衬底上的第一介电层。 通过化学机械抛光除去第二介电层，直到暴露第一​​介电层。 选择性地去除衬底上的第一介电层。

公开(公告)号：US09466497B1

公开(公告)日：2016-10-11

申请号：US14993102

申请日：2016-01-12

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Hsiang-Chen Lee ,  Yu-Chun Chang ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Yang Hsu

IPC: H01L21/336 ,  H01L29/792 ,  H01L21/28 ,  H01L27/115 ,  H01L21/027 ,  H01L21/306

CPC classification number: H01L21/28282 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1157

Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.

Abstract translation: 本发明提供一种用于制造氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法，包括：（S1）在硅衬底上形成衬垫氧化物图案，所述衬底具有露出硅的隧道区的凹部 基质; （S2），形成底部氧化物层，氮化物层，覆盖所述凹部的顶部氧化物层和所述焊盘氧化物图案以形成第一ONO结构; （S3）在覆盖所述凹部的所述第一ONO结构上形成光致抗蚀剂以及所述衬垫氧化物图案的外围区域; （S4）去除由光致抗蚀剂暴露的第一ONO结构的一部分以形成U形ONO结构; （S5）修整光致抗蚀剂以暴露在凹部上方的U形ONO结构的一部分; （S6）去除U形ONO结构的一部分; （S7）去除光致抗蚀剂; （S8）去除衬垫氧化物图案和顶部氧化物层; 和（S9）形成栅极结构。

公开(公告)号：US20160276165A1

公开(公告)日：2016-09-22

申请号：US14662142

申请日：2015-03-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： CHUEH-YANG LIU ,  YI-LIANG YE ,  TED MING-LANG GUO ,  YU-REN WANG

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31111 ,  H01L21/0206 ,  H01L21/02238 ,  H01L21/28238 ,  H01L21/823462 ,  H01L29/66545

Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).

Abstract translation: 界面氧化层形成的方法包括多个步骤。 步骤（S1）是从衬底的表面除去天然氧化物层; 步骤（S2）是通过比拉鱼溶液（SPM）在基板的表面上形成氧化物层; 步骤（S3）是通过标准清洁1（SC1）清洁氧化物层的表面，并且步骤（S4）通过包含稀释氟化氢（dHF）和臭氧化纯水（DIO3）的溶液蚀刻氧化物层 ）。

公开(公告)号：US20160268137A1

公开(公告)日：2016-09-15

申请号：US15159816

申请日：2016-05-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： CHANG-TZU WANG ,  YU-CHUN CHEN ,  TIEN-HAO TANG

IPC: H01L21/266 ,  H01L27/02 ,  H01L23/60

CPC classification number: H01L21/266 ,  H01L21/265 ,  H01L23/60 ,  H01L27/0277 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

Abstract translation: 一种制造静电放电保护结构的方法包括以下步骤。 首先，提供半导体衬底。 在半导体衬底中形成多个隔离结构，阱区，第一导电区和第二导电区。 阱区包含第一类导电载体。 第一导电区域和第二导电区域包含第二导电载体。 然后，在半导体衬底的表面上形成掩模层，其中露出第一导电区域的一部分。 然后，通过使用掩模层作为注入掩模，执行第一注入工艺以将第二类型导电载体注入阱区，使得阱区的第一类导电载体的一部分被电中和，并且第一掺杂 区域形成在第一导电区域的暴露部分下方。

公开(公告)号：US09443970B2

公开(公告)日：2016-09-13

申请号：US14924734

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hsin-Ming Hou ,  Yu-Cheng Tung ,  Ji-Fu Kung ,  Wai-Yi Lien ,  Ming-Tsung Chen

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/76224 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.

Abstract translation: 提供了包括衬底，多个隔离结构，至少栅极结构，多个虚拟栅极结构和多个外延结构的半导体器件。 衬底具有由设置在衬底内的隔离结构限定的有源区域。 也就是说，在隔离结构之间限定有源区。 栅极结构设置在基板上并且位于有源区域内。 虚拟栅极结构设置在基板上并且位于有源区域之外。 每个虚拟栅极结构的边缘与有效区域的边界分开，距离小于135埃。 外延结构被布置在栅极结构的两侧的有源区域内和衬底的一部分中。 本发明还提供了一种制造半导体器件的方法。

公开(公告)号：US09391177B1

公开(公告)日：2016-07-12

申请号：US14825174

申请日：2015-08-13

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chu-Ming Ma ,  Chun-Yi Lin ,  Hung-Chi Huang ,  Hsien-Ta Chung

IPC: H01L21/76 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11521

Abstract: The present invention provides a method for improving gate coupling ratio of a flash memory device and a protruding floating gate is formed. First, a substrate having a plurality of isolation structures is formed. Then, a first conductive layer is formed overlaying the substrate. A chemical-mechanical polishing process is performed to planarize the first conductive layer. After that, a portion of the isolation structures is removed, and a second conductive layer is formed overlaying the first conductive layer and the isolation structures. Finally, a lithography process with a photomask can be used to define a mask that covers the first conductive layer and the second conductive layer, and then an insulating layer is deposited overlaying the substrate, so that a third conductive layer is formed overlaying the insulating layer.

Abstract translation: 本发明提供了一种改善闪存器件的栅极耦合比的方法，并且形成了突出的浮置栅极。 首先，形成具有多个隔离结构的基板。 然后，形成覆盖基板的第一导电层。 进行化学机械抛光工艺以使第一导电层平坦化。 之后，去除一部分隔离结构，并且形成覆盖第一导电层和隔离结构的第二导电层。 最后，可以使用具有光掩模的光刻工艺来限定覆盖第一导电层和第二导电层的掩模，然后沉积覆盖基板的绝缘层，从而形成覆盖绝缘层的第三导电层 。

公开(公告)号：US09385191B2

公开(公告)日：2016-07-05

申请号：US14549523

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Wen-Jiun Shen ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

IPC: H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0649 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/7856

Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.

Abstract translation: 提供FINFET结构。 FINFET结构包括衬底，PMOS元件，NMOS元件，STI结构和凸块结构。 基板包括与第一区域相邻的第一区域和第二区域。 PMOS元件设置在衬底的第一区域中，并且包括至少一个第一鳍结构。 NMOS元件设置在衬底的第二区域中并且包括至少一个第二鳍结构。 STI结构设置在第一翅片结构和第二翅片结构之间。 凸块结构设置在STI结构上并具有含碳介电材料。