公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

公开(公告)号：US10185092B1

公开(公告)日：2019-01-22

申请号：US16032705

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/34 ,  G02B6/42 ,  G02B6/124

Abstract: Structures for grating couplers and methods of fabricating a structure including grating couplers. A first grating coupler includes a first plurality of grating structures. An interconnect structure includes a first metallization level that is positioned over the first grating coupler. A second grating coupler includes a second plurality of grating structures that are arranged in the first metallization level to overlap with the first grating coupler. The second plurality of grating structures are composed of a metal.

公开(公告)号：US20180233413A1

公开(公告)日：2018-08-16

申请号：US15950291

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/02 ,  H01L29/165

CPC classification number: H01L21/823431 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

公开(公告)号：US09864132B1

公开(公告)日：2018-01-09

申请号：US15282320

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roderick A. Augur ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/12 ,  H01L23/373 ,  H01L27/092

CPC classification number: G02B6/12 ,  G02B2006/12061 ,  G02B2006/12135 ,  H01L23/373 ,  H01L23/3733 ,  H01L23/3738 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon waveguide devices in integrated photonics and methods of manufacture. The integrated photonics structure includes: a localized region of negative thermal expansion (NTE) coefficient material formed within a trench; at least one photonics or CMOS component contacting with the negative thermal expansion (NTE) coefficient material; and cladding material formed above the at least one photonics or CMOS component.

公开(公告)号：US09741622B2

公开(公告)日：2017-08-22

申请号：US14608902

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of insulating material, forming an initial strain relaxed buffer layer such that it only partially fills the replacement fin cavities, implanting carbon into the initial strain relaxed buffer layer in the NMOS region, forming a channel semiconductor material on the initial strain relaxed buffer layer within the replacement fin cavities in both the NMOS region and the PMOS region to thereby define an NMOS fin comprised of the channel semiconductor material and a carbon-doped strain relaxed buffer layer and a PMOS fin comprised of the channel semiconductor material and the initial strain relaxed buffer layer and forming gate structures for the NMOS and PMOS devices.

公开(公告)号：US09634123B2

公开(公告)日：2017-04-25

申请号：US14676909

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7854

Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.

公开(公告)号：US09633947B2

公开(公告)日：2017-04-25

申请号：US14608337

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/20 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53276 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2221/1094

Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.

公开(公告)号：US09590040B2

公开(公告)日：2017-03-07

申请号：US14341000

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/84 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial fin structure above a semiconductor substrate, forming a layer of insulating material around the sacrificial fin structure, removing the sacrificial fin structure so as to define a replacement fin cavity in the layer of insulating material that exposes an upper surface of the substrate, forming a replacement fin in the replacement fin cavity on the exposed upper surface of the substrate, recessing the layer of insulating material, and forming a gate structure around at least a portion of the replacement fin exposed above the recessed layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲鳍结构，在牺牲鳍结构周围形成绝缘材料层，去除牺牲鳍结构，以便在 绝缘材料，其暴露衬底的上表面，在所述衬底的暴露的上表面上的替换翅片腔中形成替换翅片，使所述绝缘材料层凹陷，以及在所述替换鳍片的至少一部分周围形成栅极结构 暴露在绝缘材料的凹陷层上方。

公开(公告)号：US09478663B2

公开(公告)日：2016-10-25

申请号：US14526617

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Yi Qi ,  Sylvie Mignot

IPC: H01L21/336 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/18 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/324 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract translation: 一种方法包括在半导体衬底上形成翅片并在翅片的侧壁上形成凹槽。 凹槽中形成硅合金材料。 进行热处理以从硅合金材料和翅片限定硅合金翅片部分。 半导体器件包括衬底，限定在衬底上的翅片和邻近翅片设置的隔离结构。 在隔离结构上方延伸的翅片的第一部分具有基本上垂直的侧壁和不同于在隔离结构上方延伸的翅片的第二部分的不同材料组成。

公开(公告)号：US20160190339A1

公开(公告)日：2016-06-30

申请号：US15065998

申请日：2016-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ajey Poovannummoottil Jacob

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material.

Abstract translation: 半导体器件包括源极/漏极区域，栅极结构，位于栅极结构上方的栅极盖层和邻近栅极结构的相对侧定位的侧壁间隔物。 第一外延半导体材料位于源极/漏极区域中，第一外延半导体材料在其上表面具有第一横向宽度。 第二外延半导体材料定位在第一外延半导体材料上，第二外延半导体材料横向延伸并覆盖侧壁间隔物的最上端的至少一部分，并且在其上表面具有更大的第二横向宽度 比第一横向宽度。 金属硅化物区域位于第二外延半导体材料的上表面上。