公开(公告)号：US20190343017A1

公开(公告)日：2019-11-07

申请号：US15970420

申请日：2018-05-03

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H05K7/20 ,  H01L23/427 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.

公开(公告)号：US20190326192A1

公开(公告)日：2019-10-24

申请号：US15957437

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: A heat dissipation device may be formed as a thermally conductive structure having at least one thermal isolation structure extending at least partially through the thermally conductive structure. The heat dissipation device may be thermally connected to a plurality of integrated circuit devices, such that the at least one thermal isolation structure is positioned between at least two integrated circuit devices. The heat dissipation device allows for heat transfer away from each of the plurality of integrated circuit devices, such as in a z-direction within the thermally conductive structure, while substantially preventing heat transfer in either the x-direction and/or the y-direction within the thermally isolation structure, such that thermal cross-talk between integrated circuit devices is reduced.

公开(公告)号：US09807866B2

公开(公告)日：2017-10-31

申请号：US14954632

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Adel Elsherbini ,  Robert L. Sankman ,  Kemal Aygun

IPC: H05K1/02 ,  H05K9/00 ,  H05K1/18

CPC classification number: H05K1/0216 ,  H01L23/552 ,  H05K1/025 ,  H05K1/181 ,  H05K3/284 ,  H05K2203/1322 ,  Y02P70/611

Abstract: An electronic package having a substrate that includes signal traces and ground traces; an electronic component mounted on an upper surface of the substrate such that the electronic component is electrically connected to the signal traces and the ground traces in the substrate; an insulating layer covering the electronic component and the upper surface of the substrate; and an electromagnetic interference shielding mold covering the insulation layer such that the electromagnetic interference shielding mold is electrically connected to the ground traces in the substrate. In some forms of the electronic package, the electromagnetic interference shielding mold is electrically connected to the ground traces through openings in the insulation layer.

公开(公告)号：US20170179612A1

公开(公告)日：2017-06-22

申请号：US15453327

申请日：2017-03-08

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Adel Elsherbini

IPC: H01Q21/22 ,  H01Q21/00

CPC classification number: H01Q21/22 ,  G06K19/077 ,  H01L24/20 ,  H01L24/82 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15321 ,  H01Q21/0025 ,  H01Q21/0087 ,  H01Q21/0093 ,  H01Q21/065 ,  H01Q23/00

Abstract: Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length.

公开(公告)号：US20250112188A1

公开(公告)日：2025-04-03

申请号：US18478923

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Georgios C. Dogiamis ,  Qiang Yu ,  Adel Elsherbini ,  Tushar Kanti Talukdar ,  Thomas L. Sounart

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

Abstract: Methods of selectively transferring integrated circuit (IC) components between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a release layer and a layer of IC components over the release layer is received, and a second substrate with one or more adhesive areas is received. The layer of IC components may include one or more antennas, interconnects, inductors, capacitors, or transformers. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.

公开(公告)号：US12170244B2

公开(公告)日：2024-12-17

申请号：US16914062

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Henning Braunisch ,  Beomseok Choi ,  William J. Lambert ,  Stephen Morein ,  Ahmed Abou-Alfotouh ,  Johanna Swan

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H05K1/11 ,  H05K3/14

Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

公开(公告)号：US20240355725A1

公开(公告)日：2024-10-24

申请号：US18762484

申请日：2024-07-02

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Beomseok Choi ,  Henning Braunisch ,  William Lambert ,  Krishna Bharath ,  Johanna Swan

IPC: H01L23/50 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/481 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H05K1/181 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/18161

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

公开(公告)号：US12087682B2

公开(公告)日：2024-09-10

申请号：US16907797

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Beomseok Choi ,  Henning Braunisch ,  William Lambert ,  Krishna Bharath ,  Johanna Swan

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/50 ,  H01L25/00 ,  H01L25/065 ,  H05K1/18

CPC classification number: H01L23/50 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/481 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H05K1/181 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/18161

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

公开(公告)号：US20240274542A1

公开(公告)日：2024-08-15

申请号：US18628525

申请日：2024-04-05

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US12014990B2

公开(公告)日：2024-06-18

申请号：US18132865

申请日：2023-04-10

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.