公开(公告)号：US20130012010A1

公开(公告)日：2013-01-10

申请号：US13617575

申请日：2012-09-14

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Keith Kwong Hon Wong

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Keith Kwong Hon Wong

IPC分类号： H01L21/28

CPC分类号： H01L29/518 ,  H01L27/24 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a substrate and a gate stack disposed on the substrate. An upper layer of the gate stack is a metal gate conductor and a lower layer of the gate stack is a gate dielectric. A gate contact is in direct contact with the metal gate conductor.

摘要翻译： 半导体器件包括衬底和设置在衬底上的栅极堆叠。 栅极堆叠的上层是金属栅极导体，栅极叠层的下层是栅极电介质。 栅极触点与金属栅极导体直接接触。

公开(公告)号：US20120299118A1

公开(公告)日：2012-11-29

申请号：US13560240

申请日：2012-07-27

申请人： Dechao Guo ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Keith Kwong Hon Wong

IPC分类号： H01L27/088

CPC分类号： H01L29/78696 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795

摘要： A field effect transistor device includes a first conductive channel disposed on a substrate, a second conductive channel disposed on the substrate, a first gate stack formed on the first conductive channel, the first gate stack including a metallic layer having a first oxygen content, a second gate stack a formed on the second conductive channel, the second gate stack including a metallic layer having a second oxygen, an ion doped source region connected to the first conductive channel and the second conductive channel, and an ion doped drain region connected to the first conductive channel and the second conductive channel.

摘要翻译： 场效应晶体管器件包括设置在衬底上的第一导电沟道，设置在衬底上的第二导电沟道，形成在第一导电沟道上的第一栅极叠层，第一栅叠层包括具有第一氧含量的金属层， 形成在第二导电沟道上的第二栅极堆叠a，第二栅极堆叠包括具有第二氧的金属层，连接到第一导电沟道和第二导电沟道的离子掺杂源区，以及连接到第二导电沟的离子掺杂漏极区 第一导电沟道和第二导电沟道。

公开(公告)号：US08095230B2

公开(公告)日：2012-01-10

申请号：US12145025

申请日：2008-06-24

申请人： Xu Ouyang ,  Oleg Gluschenkov ,  Yunsheng Song ,  Keith Kwong Hon Wong

发明人： Xu Ouyang ,  Oleg Gluschenkov ,  Yunsheng Song ,  Keith Kwong Hon Wong

IPC分类号： G06F19/00 ,  G01N37/00 ,  H01L21/00

CPC分类号： H01L21/67276

摘要： A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots.

摘要翻译： 一种用于提高半导体制造中的总体产量的方法，包括基于从晶片或晶片批次获得的工艺变化数据，以及从处理晶片或晶片批次的工具获得的工艺变化数据布置晶片或晶圆批次。 用于提高半导体制造中的总产量的系统包括用于基于从晶片或晶片批次获得的工艺变化数据以及从处理晶片或晶片批次的工具获得的工艺变化数据来布置晶片或晶片批次的模块。

公开(公告)号：US20110248321A1

公开(公告)日：2011-10-13

申请号：US12757201

申请日：2010-04-09

申请人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

发明人： Dechao Guo ,  Wilfried E. Haensch ,  Xinhui Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28525 ,  H01L21/76897 ,  H01L21/78 ,  H01L29/66545

摘要： A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.

摘要翻译： 一种用于形成场效应晶体管的方法，包括：形成栅极叠层，与栅叠层的相对侧相邻的间隔物，在间隔物的相对侧上的硅化物源区和硅化物漏极区，在源区上外延生长硅， 漏区; 在栅极堆叠和间隔物上形成衬垫层，去除衬里层的一部分以露出硬掩模层的一部分，去除硬掩模层的暴露部分以暴露栅堆叠的硅层，将暴露的硅去除 暴露栅叠层，源极区和漏区的金属层的一部分; 以及在栅叠层，硅化物源区和硅化物漏极区的金属层上沉积导电材料。

公开(公告)号：US07973409B2

公开(公告)日：2011-07-05

申请号：US11625576

申请日：2007-01-22

申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

公开(公告)号：US20110095379A1

公开(公告)日：2011-04-28

申请号：US12607110

申请日：2009-10-28

申请人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

发明人： Keith Kwong Hon Wong ,  Dechao Guo ,  Unoh Kwon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/511 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

摘要翻译： 提供一种形成p型半导体器件的方法，其在一个实施例中使用含铝的阈值电压移位层，以产生朝向p型半导体器件的价带的阈值电压偏移。 形成p型半导体器件的方法可以包括在衬底上形成栅极结构，其中栅极结构包括与衬底接触的栅极电介质层，存在于栅极电介质层上的含铝的阈值电压移位层， 以及与含铝的阈值电压移位层和栅极电介质层中的至少一个接触的含金属层。 P型源极和漏极区可以形成在衬底附近，栅极结构所在的衬底的相邻部分。 还提供了通过上述方法提供的p型半导体器件。

公开(公告)号：US20110012629A1

公开(公告)日：2011-01-20

申请号：US12503116

申请日：2009-07-15

申请人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

发明人： Satya N. Chakravarti ,  Dechao Guo ,  Chuck T. Le ,  Byoung W. Min ,  Rajeevakumar V. Thekkemadathil ,  Keith Kwong Hon Wong

IPC分类号： G01R27/08 ,  H01L27/06 ,  H01L21/28 ,  H01H37/76

CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

摘要翻译： 在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。 第一导电材料层和无定形金属氧化物沉积到凹陷区域中。 第二导电材料层填充凹部。 在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。 为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。 感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

公开(公告)号：US07867895B2

公开(公告)日：2011-01-11

申请号：US11858166

申请日：2007-09-20

申请人： Chih-Chao Yang ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the structure are provided. The method includes the uses of at least one infusion process that forms an infused surface region within a conductive material of a lower interconnect level. The infused surface region has a different etch rate as compared with the conductive material and thus in a subsequent etching process, the infused surface region can be selectively removed forming a gouging feature within the structure.

摘要翻译： 包括通孔开口底部的气流特征的互连结构及其形成方法，其不引入由Ar溅射引入到包括通孔和线路开口的电介质材料中的损伤，也不会将空隙电镀到结构中 被提供。 该方法包括使用至少一个在较低互连级别的导电材料内形成输注表面区域的输注过程。 输入的表面区域与导电材料相比具有不同的蚀刻速率，因此在随后的蚀刻工艺中，可以选择性地去除输注的表面区域，从而在结构内形成气蚀特征。

公开(公告)号：US20110003473A1

公开(公告)日：2011-01-06

申请号：US12881806

申请日：2010-09-14

申请人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

发明人： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849

摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

摘要翻译： 提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。 此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

公开(公告)号：US07851885B2

公开(公告)日：2010-12-14

申请号：US11847379

申请日：2007-08-30

申请人： Deok-kee Kim ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Deok-kee Kim ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.

摘要翻译： 一种电可编程保险丝，包括阴极构件，阳极构件和连接构件，其中所述阴极构件，所述阳极构件和所述连接构件各自包括可操作地定位所述可编程熔丝中的感应电迁移的多种材料中的一种。