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    SOLID STATE LIGHTING DEVICES GROWN ON SEMI-POLAR FACETS AND ASSOCIATED METHODS OF MANUFACTURING
    111.
    发明申请
    SOLID STATE LIGHTING DEVICES GROWN ON SEMI-POLAR FACETS AND ASSOCIATED METHODS OF MANUFACTURING 有权
    固体照明装置在半极性表面和相关的制造方法

    公开(公告)号：US20130252365A1

    公开(公告)日：2013-09-26

    申请号：US13897922

    申请日：2013-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Zaiyuan Ren

    IPC: H01L33/32

    CPC classification number: H01L33/32 ,  H01L33/16 ,  H01L33/20 ,  H01L33/24

    Abstract: Solid state lighting devices grown on semi-polar facets and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state light device includes a light emitting diode with an N-type gallium nitride (“GaN”) material, a P-type GaN material spaced apart from the N-type GaN material, and an indium gallium nitride (“InGaN”)/GaN multi quantum well (“MQW”) active region directly between the N-type GaN material and the P-type GaN material. At least one of the N-type GaN, InGaN/GaN MQW, and P-type GaN materials is grown a semi-polar sidewall.

    Abstract translation: 本文公开了在半极面上生长的固态照明装置和相关的制造方法。 在一个实施例中，固态光器件包括具有N型氮化镓（“GaN”）材料的发光二极管，与N型GaN材料间隔开的P型GaN材料和氮化铟镓（ “InGaN”）/ GaN多量子阱（“MQW”）有源区直接在N型GaN材料和P型GaN材料之间。 N型GaN，InGaN / GaN MQW和P型GaN材料中的至少一种生长为半极性侧壁。

    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    113.
    发明公开
    MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20240088031A1

    公开(公告)日：2024-03-14

    申请号：US17930656

    申请日：2022-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Lifang Xu ,  Bo Zhao ,  Jeffrey D. Runia ,  Nancy M. Lomeli

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

    CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

    Abstract: A microelectronic device includes a stack structure including a block region and a non-block region. The block region includes blocks separated from one another in a first horizontal direction by insulative slot structures and each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks has stadium structures individually including staircase structures having steps comprising edges of some of the tiers. The non-block region neighbors the block region in the first horizontal direction. The non-block region includes additional stadium structures individually terminating at a relatively higher vertical position within the stack structure than at least one of the stadium structures at least partially within boundaries thereof in a second horizontal direction orthogonal to the first horizontal direction. Related memory devices, electronic systems, and methods are also described.

    Microelectronic devices, memory devices, and electronic systems
    115.
    发明授权
    Microelectronic devices, memory devices, and electronic systems 有权

    公开(公告)号：US11917817B2

    公开(公告)日：2024-02-27

    申请号：US17125200

    申请日：2020-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

    IPC: H10B43/50 ,  H10B41/27 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H10B43/27

    Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

    Transition structures for three-dimensional memory arrays
    118.
    发明授权
    Transition structures for three-dimensional memory arrays 有权

    公开(公告)号：US11756596B1

    公开(公告)日：2023-09-12

    申请号：US17752332

    申请日：2022-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Lifang Xu

    IPC: G11C7/18 ,  G11C7/10 ,  H01L25/065 ,  H01L23/48 ,  H10B99/00

    CPC classification number: G11C7/18 ,  G11C7/1027 ,  H01L23/481 ,  H01L25/0652 ,  H10B99/00

    Abstract: Methods, systems, and devices for transition structures for three-dimensional memory arrays are described. A memory device may include a staircase region which includes a set of vias. The set of vias may include a first subset of vias which couple respective word line plates of the memory region with associated word line decoders, and a second subset of vias which are electrically isolated from the word line plates. The second subset of vias may be arranged in one or more rows positioned between the first subset of vias and the memory region. In some cases, the second subset of vias may be positioned above respective conductive contacts. Additionally or alternatively, the second subset of vias may be positioned above a common conductor shared with pillars of the memory region.

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