公开(公告)号：US10892344B2

公开(公告)日：2021-01-12

申请号：US15981659

申请日：2018-05-16

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22 ,  H01L29/66

摘要： Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

公开(公告)号：US10700194B2

公开(公告)日：2020-06-30

申请号：US16026663

申请日：2018-07-03

申请人： STMicroelectronics, Inc.

发明人： Qing Liu ,  John H. Zhang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

摘要： A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US10546789B2

公开(公告)日：2020-01-28

申请号：US14986229

申请日：2015-12-31

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L27/092

摘要： Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

公开(公告)号：US10546743B2

公开(公告)日：2020-01-28

申请号：US15874654

申请日：2018-01-18

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

发明人： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC分类号： H01L21/02 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768

摘要： Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

公开(公告)号：US10247881B2

公开(公告)日：2019-04-02

申请号：US15491718

申请日：2017-04-19

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L21/4763 ,  G02B6/132 ,  G02B6/122 ,  H01L23/522 ,  G02B6/13 ,  H01L21/768 ,  G02B6/136 ,  H01L23/532 ,  H01L21/66 ,  G02B6/12

摘要： A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

公开(公告)号：US10242862B2

公开(公告)日：2019-03-26

申请号：US15391135

申请日：2016-12-27

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L21/02 ,  H01L21/67 ,  B08B3/08 ,  B08B3/12

摘要： A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing—rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps.

公开(公告)号：US10109505B2

公开(公告)日：2018-10-23

申请号：US15424297

申请日：2017-02-03

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： John H. Zhang ,  Laertis Economikos ,  Adam Ticknor ,  Wei-Tsu Tseng

IPC分类号： H01L21/67 ,  B01D15/36 ,  B01D24/00

摘要： The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

公开(公告)号：US10038072B2

公开(公告)日：2018-07-31

申请号：US14982316

申请日：2015-12-29

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/775 ,  H01L21/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/41 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/165

CPC分类号： H01L29/66492 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823842 ,  H01L22/12 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L2924/0002 ,  H01L2924/00

摘要： Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.

公开(公告)号：US10026849B2

公开(公告)日：2018-07-17

申请号：US15259516

申请日：2016-09-08

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC分类号： H01L21/8234 ,  H01L27/146 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/49

摘要： Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

公开(公告)号：US09997463B2

公开(公告)日：2018-06-12

申请号：US15191359

申请日：2016-06-23

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L27/06 ,  H01L29/08 ,  H01L27/07 ,  H01L27/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L23/538 ,  H01L29/417 ,  H01L29/775 ,  H01L29/792 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/51

CPC分类号： H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

摘要： A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.