公开(公告)号：US09653470B2

公开(公告)日：2017-05-16

申请号：US14671606

申请日：2015-03-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L21/28 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  G11C16/14 ,  H01L29/66 ,  H01L27/11524 ,  H01L27/11519 ,  G11C16/04

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28008 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

公开(公告)号：US09613709B2

公开(公告)日：2017-04-04

申请号：US15276462

申请日：2016-09-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/027 ,  G11C16/14 ,  H01L27/11524 ,  G11C16/08 ,  H01L27/02

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

公开(公告)号：US09570513B2

公开(公告)日：2017-02-14

申请号：US14150596

申请日：2014-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L27/108 ,  H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L29/08

CPC classification number: H01L27/2445 ,  H01L27/226 ,  H01L29/0821 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/04 ,  H01L45/06 ,  H01L45/16

Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.

Abstract translation: 本公开涉及包括晶体管的集成电路，该晶体管包括第一和第二导电端子以及控制端子。 集成电路还包括第一介电层，导电层和第二介电层的堆叠，第一导电端子包括形成在第一介电层中的第一半导体区域，该控制端子包括形成在第一介电层中的第二半导体区域 导电层，第二导电端子包括形成在第二介电层中的第三半导体区域。

公开(公告)号：US09461129B2

公开(公告)日：2016-10-04

申请号：US14854542

申请日：2015-09-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/115 ,  H01L29/78 ,  G11C16/04 ,  H01L29/66

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

Abstract translation: 形成在半导体衬底中的存储单元包括在衬底中形成的沟槽中垂直延伸的选择栅极，并且通过栅极氧化物的第一层与衬底隔离，水平浮动栅极延伸在衬底上方并与衬底隔离，并与衬底隔离 栅极氧化物的第二层和在浮置栅极上方延伸的水平控制栅极。 选择栅极覆盖浮动栅极的侧面。 浮置栅极仅由第一层栅极氧化物与选择栅极分离，并且与垂直沟道区分离，仅沿着选择栅极在衬底中延伸，仅由栅极氧化物的第二层分离。

公开(公告)号：US20160247572A1

公开(公告)日：2016-08-25

申请号：US14964196

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C16/08 ,  G11C16/14

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.

Abstract translation: 本公开涉及包括具有至少两行存储器单元的存储器阵列的存储器，耦合到第一行存储器单元的控制线的第一驱动器和耦合到第二行存储器单元的控制线的第二驱动器 记忆细胞 第一驱动器在第一阱中制造，第二驱动器在与第一阱电绝缘的第二阱中制造，并且两行存储器单元在与第一阱和第二阱良好地电绝缘的存储器阵列中产生。

公开(公告)号：US20160181265A1

公开(公告)日：2016-06-23

申请号：US14854542

申请日：2015-09-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Jean-Michel Mirabel ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  G11C16/14 ,  G11C16/04

CPC classification number: H01L29/42336 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7889

Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.

公开(公告)号：US20160064089A1

公开(公告)日：2016-03-03

申请号：US14795742

申请日：2015-07-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased.

Abstract translation: 非易失性存储器包括位线，包括第一类型的存储器单元的第一可寻址扇区和包括第二类型的存储单元的第二可擦除或可位可擦除扇区。 第一类型的存储单元包括单个浮栅晶体管，并且第二类型的存储单元包括第一浮栅晶体管和浮置栅电耦合的第二浮栅晶体管，第二浮栅 第二种类型的存储器单元的晶体管使得能够单独地擦除存储单元。

公开(公告)号：US20150348981A1

公开(公告)日：2015-12-03

申请号：US14671606

申请日：2015-03-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L21/28 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  G11C16/14 ,  H01L29/66

CPC classification number: H01L27/11524 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28008 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7889 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储器，包括：第一存储单元，包括浮栅晶体管和具有嵌入垂直控制栅极的选择晶体管，第二存储单元包括浮栅晶体管和 选择具有与第一存储单元的选择晶体管相同的控制栅极的晶体管，耦合到第一存储单元的浮置栅晶体管的第一位线和耦合到第二存储器的浮置栅极晶体管的第二位线 细胞。

公开(公告)号：US20150130502A1

公开(公告)日：2015-05-14

申请号：US14599116

申请日：2015-01-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa

IPC: G01R31/28 ,  G11C11/412 ,  G11C5/06 ,  G01R31/40

CPC classification number: G01R31/282 ,  G01R31/40 ,  G06F21/552 ,  G06F21/554 ,  G06F21/75 ,  G06F21/77 ,  G11C5/06 ,  G11C11/412 ,  G11C11/417

Abstract: A device for detecting a fault attack, including: a circuit for detecting an interruption of a power supply; a circuit for comparing the duration of said interruption with a first threshold; and a counter of the number of successive interruptions of the power supply having a duration which does not exceed the first threshold.

Abstract translation: 一种用于检测故障攻击的装置，包括：用于检测电源中断的电路; 用于将所述中断的持续时间与第一阈值进行比较的电路; 以及具有不超过第一阈值的持续时间的电源的连续中断次数的计数器。

公开(公告)号：US09012961B2

公开(公告)日：2015-04-21

申请号：US14148257

申请日：2014-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Hélène Dalle-Houilliez

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/78 ,  H01L29/66 ,  G11C16/04

CPC classification number: H01L27/11556 ,  G11C16/0433 ,  H01L27/11524 ,  H01L29/66666 ,  H01L29/7827

Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.

Abstract translation: 本公开涉及在半导体衬底中制造垂直栅极晶体管的方法，包括在衬底的深度中注入掺杂的隔离层，以形成晶体管的源极区域; 在衬底中形成垂直于沟槽隔离的平行沟槽隔离和第二沟槽，到达隔离层，并通过第一介电层与衬底隔离; 在所述衬底的表面和所述第二沟槽中沉积第一导电层; 蚀刻第一导电层以形成晶体管的垂直栅极，以及在垂直栅极的末端和衬底的边缘之间的垂直栅极连接焊盘，同时在每个连接焊盘和垂直栅极之间的第一导电层中保持连续区域 门; 以及在所述第二沟槽的每一侧上注入掺杂区域，以形成所述晶体管的漏极区域。