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900 条记录 (耗时 0.029 秒)

    Complementary MIS device
    112.
    发明授权
    Complementary MIS device 失效
    互补MIS设备

    公开(公告)号：US07566936B2

    公开(公告)日：2009-07-28

    申请号：US11606181

    申请日：2006-11-30

    申请人： Tadahiro Ohmi ,  Koji Kotani ,  Shigetoshi Sugawa

    发明人： Tadahiro Ohmi ,  Koji Kotani ,  Shigetoshi Sugawa

    IPC分类号： H01L29/76

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/66795 ,  H01L29/7851

    摘要： A CMOS device includes a p-channel MOS transistor and an n-channel MOS transistor having a structure formed on a (100) surface of a silicon substrate and having a different crystal surface, a high-quality gate insulation film formed on such a structure by a microwave plasma process, and a gate electrode formed thereon, wherein the size and the shape of the foregoing structure is set such that the carrier mobility is balanced between the p-channel MOS transistor and the n-channel MOS transistor.

    摘要翻译： CMOS器件包括具有形成在硅衬底（100）表面上并具有不同晶体表面的结构的p沟道MOS晶体管和n沟道MOS晶体管，形成在这种结构上的高质量栅极绝缘膜 通过微波等离子体处理和形成在其上的栅电极，其中上述结构的尺寸和形状被设置为使得载流子迁移率在p沟道MOS晶体管和n沟道MOS晶体管之间平衡。

    Semiconductor Device
    114.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20090166739A1

    公开(公告)日：2009-07-02

    申请号：US12085776

    申请日：2006-11-30

    申请人： Tadahiro Ohmi ,  Akinobu Teramoto

    发明人： Tadahiro Ohmi ,  Akinobu Teramoto

    IPC分类号： H01L27/092

    CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/045 ,  H01L29/785 ,  H01L2029/7857

    摘要： In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.

    摘要翻译： 为了获得形成CMOS电路的p型MOS晶体管和n型MOS晶体管的大致相同的工作速度，n型MOS晶体管具有三维结构，在（100） （110）面和p型MOS晶体管具有仅在（110）面上具有沟道区的平面结构。 此外，两个晶体管在沟道区域和栅极绝缘膜的区域中基本上彼此相等。 因此，可以使栅极绝缘膜等的面积相等并且使栅极电容彼此相等。

    Semiconductor device, method for forming silicon oxide film, and apparatus for forming silicon oxide film
    118.
    发明授权
    Semiconductor device, method for forming silicon oxide film, and apparatus for forming silicon oxide film 有权
    半导体装置，氧化硅膜的形成方法以及氧化硅膜的形成装置

    公开(公告)号：US07491656B2

    公开(公告)日：2009-02-17

    申请号：US10943841

    申请日：2004-09-20

    申请人： Tadahiro Ohmi

    发明人： Tadahiro Ohmi

    IPC分类号： H01L21/31

    CPC分类号： H01L27/1214 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/4908 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.

    摘要翻译： 用作半导体器件的栅极绝缘膜的氧化硅膜（1701）包含Kr。 因此，氧化硅膜（1701）中的应力和硅与氧化硅膜之间的界面处的应力被松弛，并且氧化硅膜即使在低温下形成也具有高质量。 元件隔离区域的槽（凹部）的侧壁的硅上的氧化硅膜（1701）的厚度的均匀度为30％以下。 因此，氧化硅膜（1701）的特性和可靠性优于硅热氧化膜，可以使元件隔离区域变小，从而实现优选适于SOI晶体管的高性能晶体管集成电路， 一个TFT。

    Semiconductor Device Manufacturing Method and Method for Reducing Microroughness of Semiconductor Surface
    119.
    发明申请
    Semiconductor Device Manufacturing Method and Method for Reducing Microroughness of Semiconductor Surface 有权
    半导体器件的制造方法和减少半导体表面微观粗糙度的方法

    公开(公告)号：US20090023231A1

    公开(公告)日：2009-01-22

    申请号：US12223385

    申请日：2007-01-30

    申请人： Tadahiro Ohmi ,  Hitoshi Morinaga

    发明人： Tadahiro Ohmi ,  Hitoshi Morinaga

    IPC分类号： H01L21/66 ,  H01L21/306 ,  B08B7/00

    CPC分类号： H01L21/02052 ,  H01L21/02074

    摘要： Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved.

    摘要翻译： 用液体进行表面处理，同时将半导体表面从光屏蔽。 当在诸如清洁，蚀刻和半导体表面的显影的湿法中使用该方法进行表面处理时，可以降低表面微粗糙度的增加。 因此，提高了半导体器件的电特性和产量。