公开(公告)号：US07087955B2

公开(公告)日：2006-08-08

申请号：US10811830

申请日：2004-03-30

申请人： Yoshiyuki Kawashima ,  Fumitoshi Ito ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama

发明人： Yoshiyuki Kawashima ,  Fumitoshi Ito ,  Takeshi Sakai ,  Yasushi Ishii ,  Yasuhiro Kanamaru ,  Takashi Hashimoto ,  Makoto Mizuno ,  Kousuke Okuyama

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66833

摘要： A semiconductor device has a nonvolatile memory employing a split-gate type memory cell structure, using a nitride film as a charge storage layer. An n-type semiconductor region is formed in a main surface of a semiconductor substrate, and then, a memory gate electrode of a memory cell of a split gate type and a charge storage layer are formed over the semiconductor region. Subsequently, side walls are formed on side surfaces of the memory gate electrode, and a photoresist pattern is formed over the main surface of the semiconductor substrate. The photoresist pattern serves as an etching mask, and a part of the main surface of the semiconductor substrate is removed by etching to form a dent. In the region of the dent, the n-type semiconductor region is removed. Then, a p-type semiconductor region for forming a channel of an nMIS transistor for selecting a memory cell is formed.

摘要翻译： 半导体器件具有使用氮化物膜作为电荷存储层的采用分离栅型存储单元结构的非易失性存储器。 在半导体衬底的主表面中形成n型半导体区域，然后在半导体区域上形成分裂栅型存储单元的存储栅电极和电荷存储层。 随后，在存储栅电极的侧表面上形成侧壁，并且在半导体衬底的主表面上形成光刻胶图形。 光致抗蚀剂图案用作蚀刻掩模，并且通过蚀刻去除半导体衬底的主表面的一部分以形成凹陷。 在凹陷的区域中，去除n型半导体区域。 然后，形成用于形成用于选择存储单元的nMIS晶体管的沟道的p型半导体区域。

公开(公告)号：US06994414B2

公开(公告)日：2006-02-07

申请号：US10275000

申请日：2002-10-22

申请人： Takashi Hashimoto ,  Masahiro Furusawa

发明人： Takashi Hashimoto ,  Masahiro Furusawa

IPC分类号： B41J29/393

CPC分类号： H05K3/125 ,  B41J3/407 ,  B41J2202/09 ,  H01L21/288 ,  H05K2203/1476

摘要： The invention provides a method for forming a film pattern, in which a method for forming a film pattern by the ink-jet method is improved, an increase in film thickness is achieved efficiently with simple steps, a requirement for a decrease in line width is met and, in addition, problems such as breaks and short circuits are not brought about when a conductive film is made. The method can include a first discharging step, wherein droplets are discharged in the whole film formation region with a pitch larger than the diameter of the droplet after being hit onto the substrate. In the second discharging step, droplets are discharged at positions in the whole film formation region different from the discharge positions in the first discharging step with the same pitch as that in the first discharging step. In the third discharging step, droplets are discharged in the whole film formation region with a pitch smaller than the pitch in the first discharging step. The substrate is treated beforehand in order to have the contact angle of 60 degrees or more with respect to the droplets.

公开(公告)号：US06964820B2

公开(公告)日：2005-11-15

申请号：US10155122

申请日：2002-05-28

申请人： Hitoshi Shimonosono ,  Takashi Hashimoto

发明人： Hitoshi Shimonosono ,  Takashi Hashimoto

IPC分类号： F24H1/18 ,  H01M8/04

CPC分类号： H01M8/04029

摘要： A water pump (4) recirculates water from a water tank (3) in a heat exchanger (2) and a fuel cell stack (1) of a fuel cell power plant via a recirculation passage (5) A water temperature sensor (13) detects a water temperature in the recirculation passage (5). When the water temperature is lower than a predetermined temperature, a controller (16) recirculates water to the water recirculation passage (5) by operating a water pump (4) in order to prevent freezing of water. It is preferred that a heater (15) is provided to heat the water recirculating in the recirculation passage (5).

摘要翻译： 水泵（4）通过再循环通道（5）将来自燃料电池发电厂的热交换器（2）中的水箱（3）和燃料电池堆（1）的水再循环。水温传感器（13） 检测再循环通道（5）中的水温。 当水温低于预定温度时，控制器（16）通过操作水泵（4）将水再循环到水再循环通道（5），以防止水的冻结。 优选地，设置加热器（15）以加热再循环通道（5）中再循环的水。

公开(公告)号：US06847108B2

公开(公告)日：2005-01-25

申请号：US10812081

申请日：2004-03-30

申请人： Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

发明人： Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/50 ,  H01L23/66 ,  H03F3/187 ,  H04B1/38 ,  H04B1/3822 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.

公开(公告)号：US20050006698A1

公开(公告)日：2005-01-13

申请号：US10852150

申请日：2004-05-25

申请人： Nozomu Matsuzaki ,  Tetsuya Ishimaru ,  Makoto Mizuno ,  Takashi Hashimoto

发明人： Nozomu Matsuzaki ,  Tetsuya Ishimaru ,  Makoto Mizuno ,  Takashi Hashimoto

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/107 ,  G11C16/3468

摘要： Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.

摘要翻译： 通过从基板注入电子并将电子提取到栅极电极进行擦除和写入操作的存储单元构成半导体非易失性存储器件。 这是一个栅极提取半导体非易失性存储器件。 在该器件中，如果在擦除和写入操作的第一过程中施加擦除偏置，则发生过度过热状态的存储器单元，并且这种存储器单元的电荷保留特性降低。 本发明提供一种半导体非易失性存储器件，其使用在施加擦除偏置之前将所有存储单元写入擦除单元的装置，然后施加擦除偏置。

公开(公告)号：US06836262B2

公开(公告)日：2004-12-28

申请号：US09782292

申请日：2001-02-14

申请人： Takashi Hashimoto ,  Takahiro Urakabe ,  Akihiko Iwata ,  Yoshikazu Tsunoda ,  Takayoshi Nagai

发明人： Takashi Hashimoto ,  Takahiro Urakabe ,  Akihiko Iwata ,  Yoshikazu Tsunoda ,  Takayoshi Nagai

IPC分类号： G09G328

CPC分类号： G09G3/2927 ,  G09G3/296 ,  G09G2310/066 ,  G09G2320/0228

摘要： In a reset period, through applying a rectangular pulse (Pya) of positive polarity to an electrode (Y) and applying a CR pulse (Pxa) of negative polarity to an electrode X, a full lighting pulse is applied between the electrodes (X and Y). The application of the voltage is stopped before a CR pulse (Pxc) reaches a final potential, to generate the pulse (Pxa). A full erase pulse (Pxb) made of a CR pulse having a polarity reverse to that of the pulse (Pxa) is applied to the electrode (X). An erase operation reverses the polarity of wall charges accumulated by a full lighting to effectively perform a potential control operation. The potential control pulse (Pxc) is applied to the electrode (X) to generate a discharge, and the state of the wall charges in a discharge cell is controlled by the discharge to generate an optimal amount of wall charges for a subsequent addressing discharge. The final voltage of the pulse (Pxc) is set equal to a voltage (−Vxg) of an address pulse (Pa). Thus, it is possible to generate a plurality of pulses and stabilize an operation of a PDP with a simple constitution.

摘要翻译： 在复位期间，通过向电极（Y）施加正极性的矩形脉冲（Pya），向电极X施加负极性的CR脉冲（Pxa），在电极（X， Y）。 在CR脉冲（Pxc）达到最终电位之前停止施加电压，以产生脉冲（Pxa）。 将由具有与脉冲（Pxa）相反极性的CR脉冲构成的完全擦除脉冲（Pxb）施加到电极（X）。 擦除操作反转由完全照明积累的壁电荷的极性，以有效地执行电位控制操作。 将电位控制脉冲（Pxc）施加到电极（X）以产生放电，并且通过放电来控制放电单元中的壁电荷的状态，以产生用于随后的寻址放电的最佳量的壁电荷。 将脉冲的最终电压（Pxc）设定为等于寻址脉冲（Pa）的电压（-Vxg）。 因此，可以以简单的结构产生多个脉冲并稳定PDP的操作。

公开(公告)号：US06833582B2

公开(公告)日：2004-12-21

申请号：US10766188

申请日：2004-01-29

申请人： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

发明人： Toshiyuki Mine ,  Takashi Hashimoto ,  Senichi Nishibe ,  Nozomu Matsuzaki ,  Hitoshi Kume ,  Jiro Yugami

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  H01L21/28282 ,  H01L29/792

摘要： A nonvolatile semiconductor memory device configured by a select MOS transistor provided with a gate insulator film and a select gate electrode, as well as a memory MOS transistor provided with a capacitor insulator film comprising a lower potential barrier film, a charge trapping film, and an upper potential barrier film, as well as a memory gate electrode. The charge trapping film is formed with a silicon oxynitride film and the upper potential barrier film is omitted or its thickness is limited to 1 nm and under to prevent the Gm degradation to be caused by the silicon oxynitride film, thereby lowering the erasure gate voltage. The charge trapping film is formed with a silicon oxynitride film used as a main charge trapping film and a silicon nitride film formed on or beneath the silicon oxynitride film so as to form a potential barrier effective only for holes. And, a hot-hole erasing method is employed to lower the erasure voltage.

公开(公告)号：US06787841B2

公开(公告)日：2004-09-07

申请号：US10650732

申请日：2003-08-29

申请人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

发明人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC分类号： H01L2976

CPC分类号： B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

摘要翻译： 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US06639310B2

公开(公告)日：2003-10-28

申请号：US10083547

申请日：2002-02-27

申请人： Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

发明人： Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

IPC分类号： H04B106

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.

摘要翻译： 一种防止低噪声放大器和接收混频器的频率特性劣化的引脚布局，包括在用于双频带发送/接收的半导体集成电路中，其中低噪声放大器的电路设置在距离 低端放大器封装外的引脚到焊盘最短; 两个低噪声放大器的接地引脚和高频信号引脚分别布置为不彼此相邻; 低噪声放大器的电源和接地引脚以及偏置电路的电源和接地引脚分别分开; 高频信号线不会相交。

公开(公告)号：US06571442B1

公开(公告)日：2003-06-03

申请号：US09593372

申请日：2000-06-15

申请人： Motoyuki Okeshi ,  Ken Taniguchi ,  Takashi Hashimoto ,  Makoto Irie ,  Hiroyuki Kawakami ,  Choichiro Fujii ,  Michinobu Maesaka ,  Hidemasa Iwami ,  Takashi Iwamoto

发明人： Motoyuki Okeshi ,  Ken Taniguchi ,  Takashi Hashimoto ,  Makoto Irie ,  Hiroyuki Kawakami ,  Choichiro Fujii ,  Michinobu Maesaka ,  Hidemasa Iwami ,  Takashi Iwamoto

IPC分类号： H04R1700

CPC分类号： H03H9/58 ,  H01L41/0475 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/4848 ,  H03H9/0514 ,  H03H9/1014 ,  H03H9/176 ,  H03H9/56 ,  H03H9/562 ,  H03H9/581 ,  Y10T29/42 ,  Y10T29/4921 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic component has a substantially reduced size and is adapted to be produced at low costs without variation in superior quality of the component because of the ease of achieving electrical connection between a piezoelectric element and a electrode pattern on a substrate supporting the piezoelectric element. The piezoelectric element has a lower electrode formed on the lower surface thereof and an upper electrode formed on the upper surface thereof. The piezoelectric element is fixed to the substrate such that the lower electrode is bonded to an electrode provided on the substrate by a conductive adhesive. A conductive wire is fixed to the upper electrode of the piezoelectric element. A metallic cap is bonded to the substrate so as to cover and seal the piezoelectric element on the substrate. The cap is contacted at its inner surface by the wire, whereby an electrical connection is achieved between the cap and the upper electrode of the piezoelectric element. Input and output lead terminals are connected to the electrodes on the substrate, while a grounding lead terminal is connected to the cap.

摘要翻译： 电子部件具有基本上减小的尺寸，并且适于以低成本生产，而不会由于在支撑压电元件的基板上实现压电元件和电极图案之间的电连接而容易地实现元件的优良品质。 压电元件具有形成在其下表面上的下电极和形成在其上表面上的上电极。 压电元件固定到基板上，使得下电极通过导电粘合剂结合到设置在基板上的电极。 导电线固定在压电元件的上电极上。 将金属盖结合到基板上，以覆盖并密封基板上的压电元件。 盖通过导线在其内表面处接触，从而在盖和压电元件的上电极之间实现电连接。 输入和输出引线端子连接到基板上的电极，而接地引线端子连接到盖子。