公开(公告)号：US10468456B2

公开(公告)日：2019-11-05

申请号：US15898562

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.

公开(公告)号：US10468310B2

公开(公告)日：2019-11-05

申请号：US15334964

申请日：2016-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

公开(公告)号：US10468083B1

公开(公告)日：2019-11-05

申请号：US16010841

申请日：2018-06-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob

IPC: G11C5/06 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01L43/12 ,  H01L43/10

Abstract: Integrated circuits and methods of operating and producing the same are provided. In an exemplary embodiment, an integrated circuit includes a look up table with a first and second memory cell. The first memory cell includes a first magneto electric (ME) layer, a first free layer adjacent to the first ME layer, and a first fixed layer. The second memory cell includes a second ME layer, a second free layer adjacent to the second ME layer, and a second fixed layer. A first word line is in direct communication with the first and second free layers, wherein direct communication is a connection through zero, one, or more intervening components that are electrical conductors. A first bit line is in direct communication with the first ME layer, and a second bit line is in direct communication with the second ME layer.

公开(公告)号：US10466514B1

公开(公告)日：2019-11-05

申请号：US16181879

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02F1/035 ,  G02F1/225 ,  G02B6/122 ,  G02B6/136 ,  F21V8/00 ,  G02F1/015 ,  G02F1/21 ,  G02B6/12

Abstract: Structures for an electro-optic modulator and methods of fabricating such structures. A first plurality of cavities are formed in a bulk semiconductor substrate. A passive waveguide arm includes a first core arranged over the first plurality of cavities. The passive waveguide arm has an input port and an output port that is spaced lengthwise from the input port. An epitaxial semiconductor layer is arranged over the bulk semiconductor substrate, and includes a second plurality of cavities. An active waveguide arm includes a second core that is arranged over the second plurality of cavities. The second core of the active waveguide arm is coupled with the input port of the first core of the passive waveguide arm, and the second core of the active waveguide arm is also coupled with the output port of the first core of the passive waveguide arm.

公开(公告)号：US20190333814A1

公开(公告)日：2019-10-31

申请号：US16503706

申请日：2019-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark L. LENHARDT ,  Frank W. MONT ,  Brown C. PEETHALA ,  Shariq SIDDIQUI ,  Jessica P. STRISS ,  Douglas M. TRICKETT

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

公开(公告)号：US10461173B1

公开(公告)日：2019-10-29

申请号：US15990186

申请日：2018-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Xuan Anh Tran ,  Hui Zang ,  Bala Haran ,  Suryanarayana Kalaga

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor (vFET) including top and bottom source/drain regions produced in one epitaxial growth process. The vFET may contain a semiconductor substrate; a fin above the semiconductor substrate; a structure on a middle portion of each sidewall of the fin, wherein a lower portion of each sidewall of the fin adjacent the semiconductor substrate and at least a top of the fin are uncovered by the structure; a top source/drain (S/D) region on at least the top of the fin; and a bottom S/D region on the lower portion of the fin and the semiconductor substrate. The structure on each sidewall may be a gate or a dummy gate, i.e., the vFET may be formed in a gate-first or a gate-last process.

公开(公告)号：US10461029B2

公开(公告)日：2019-10-29

申请号：US15686230

申请日：2017-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu Wong ,  Jagar Singh

IPC: H01L23/525 ,  H01L23/528 ,  H01L21/762 ,  H01L29/161

Abstract: Methods of forming a hybrid electrically programmable fuse (e-fuse) structure and the hybrid e-fuse structure are disclosed. In various embodiments, the e-fuse structure includes: a substrate; an insulator layer over the substrate; a pair of contact regions overlying the insulator layer; and a silicide channel overlying the insulator layer and connecting the pair of contact regions, the silicide channel having a first portion including silicide silicon and a second portion coupled with the first portion and on a common level with the first portion, the second portion including silicide silicon germanium (SiGe) or silicide silicon phosphorous (SiP).

公开(公告)号：US10460986B2

公开(公告)日：2019-10-29

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Chih-Chiang Chang ,  Michael Aquilino ,  Patrick Carpenter ,  Junsic Hong ,  Mitchell Rutkowski ,  Haigou Huang ,  Huy Cao

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10460067B2

公开(公告)日：2019-10-29

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/30 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L21/762 ,  H01L27/118

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

公开(公告)号：US20190319112A1

公开(公告)日：2019-10-17

申请号：US15951621

申请日：2018-04-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/02

Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.