公开(公告)号：US20200264652A1

公开(公告)日：2020-08-20

申请号：US16276744

申请日：2019-02-15

申请人： Wisconsin Alumni Research Foundation

发明人： Gokul Subramanian Ravi ,  Mikko H. Lipasti

IPC分类号： G06F1/10 ,  G06F9/38

摘要： A computer architecture suitable for out-of-order processors manages the problem of timing slack, in which an instruction completes before its clock cycle, by recycling that slack to allow the next succeeding instruction allowing that instruction to begin execution earlier. This recycling mechanism is enabled through the use of a transparent gating between execution units which allows data transfer before clock cycle boundaries and, in some cases, by aggressively issuing children instructions contemporaneously with their parent instruction after a grandparent instruction is issued.

公开(公告)号：US10749535B2

公开(公告)日：2020-08-18

申请号：US16011970

申请日：2018-06-19

申请人： Analog Devices, Inc.

发明人： Reuben P. Nelson ,  Neil E. Weeks

IPC分类号： G06F1/12 ,  H03L7/081 ,  H03L7/08 ,  G06F1/10 ,  H03L7/10 ,  H04B1/16 ,  H03K5/00

摘要： Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US20200244274A1

公开(公告)日：2020-07-30

申请号：US16261161

申请日：2019-01-29

申请人： UNIVERSITY OF WASHINGTON

发明人： Visvesh S. Sathe

IPC分类号： H03L7/091 ,  H03K3/03 ,  H03L7/089 ,  G06F1/10 ,  G06F5/06

摘要： A control circuit includes a digital load, a voltage conversion circuit configured to provide a supply voltage to the digital load, an oscillator configured to provide, to the digital load, a clock signal having an oscillation frequency that (i) depends on the supply voltage and (ii) is less than a reciprocal of a critical path delay of the digital load, and a phase detector configured to provide, to the voltage conversion circuit, a phase signal that is indicative of a phase difference between the clock signal and a reference signal. The voltage conversion circuit is further configured to adjust the supply voltage based on the phase signal such that the oscillator changes the oscillation frequency to reduce the phase difference.

公开(公告)号：US20200226094A1

公开(公告)日：2020-07-16

申请号：US16833068

申请日：2020-03-27

申请人： Altera Corporation

发明人： Chee Hak Teh ,  Arifur Rahman

IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US10705738B2

公开(公告)日：2020-07-07

申请号：US16035703

申请日：2018-07-15

申请人： Shanghai Xiaoyi Technology Co., Ltd.

发明人： Jinsuo Yu ,  Xuewu Zhang

IPC分类号： G06F3/06 ,  H03K5/14 ,  H03K5/135 ,  H03K3/86 ,  H03K5/131 ,  G06F1/10 ,  G11C7/22

摘要： Embodiments of the disclosure provide a method, apparatus, and computer readable medium for optimizing memory card performance. The method includes: determining a plurality of different preset time intervals, the preset time intervals being determined beginning from clock-cycle starting points; sending test data to a memory card using each of the preset time intervals, respectively; reading from the memory card the test data corresponding to each of the preset time intervals; comparing the test data sent using each of the preset time intervals with the corresponding test data that is read; in response to the sent test data and the read test data being consistent, determining that the preset time interval is valid; determining at least one group of preset time intervals, each of the groups of preset time intervals containing a plurality of valid and successive preset time intervals; determining a group of preset time intervals containing a maximum number of preset time intervals as a target group; determining an average value of all the preset time intervals in the target group as a time interval for writing to the memory card.

公开(公告)号：US10686582B1

公开(公告)日：2020-06-16

申请号：US16285056

申请日：2019-02-25

申请人： Intel Corporation

发明人： Gerald Pasdast ,  Nasser A. Kurd ,  Peipei Wang ,  Yingyu Miao ,  Lakshmipriya Seshan ,  Ishaan S. Shah

IPC分类号： H04L7/00 ,  H03L7/081 ,  H03L7/093 ,  H03K5/00 ,  G06F1/08 ,  G06F1/10 ,  G06F1/06 ,  H03K3/037

摘要： An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.

公开(公告)号：US20200176158A1

公开(公告)日：2020-06-04

申请号：US16206014

申请日：2018-11-30

申请人： JOSHUA A. STRONG

发明人： JOSHUA A. STRONG

IPC分类号： H01F6/06 ,  H01P3/08 ,  H03K19/195 ,  H01P11/00 ,  H01F41/04 ,  H01L27/18 ,  H01L23/66 ,  G06F1/10

摘要： A superconducting on-chip coiled coupled-line 90° hybrid coupler is made of a series array of repeated cells of coiled transmission lines that are inductively and capacitively coupled. The coupler splits an incoming microwave signal into two output signals of roughly equal power and separated in phase from each other by roughly 90°. The coupler can be incorporated into such superconducting electronic circuits as clock-distribution networks for reciprocal quantum logic (RQL) systems, as well as Josephson-based phase shifters and vector modulators.

公开(公告)号：US10671564B2

公开(公告)日：2020-06-02

申请号：US15090722

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. Glenn Henry ,  Terry Parks ,  Kyle T. O'Brien

IPC分类号： G06F15/82 ,  G06F9/30 ,  G06F9/32 ,  G06F1/10 ,  G06F9/38 ,  G06N3/04 ,  G06F9/445 ,  G06N3/063 ,  G06N3/08 ,  G06F7/499 ,  G06F7/483

摘要： A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units (NPU) each have a multiplexed register that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU. A register receives a corresponding element of a row from the second memory. An arithmetic unit receives the outputs of the register, the multiplexed register and an accumulator and performs a multiply-accumulate operation on them. For each sub-matrix of a plurality of sub-matrices of the data matrix, each arithmetic unit selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel.

公开(公告)号：US20200169251A1

公开(公告)日：2020-05-28

申请号：US16199548

申请日：2018-11-26

申请人： International Business Machines Corporation

发明人： Andreas H.A. Arp ,  Fatih Cilek ,  Michael V. Koch ,  Thomas Makowski ,  Matthias Ringe

IPC分类号： H03K5/19 ,  H03K5/1534 ,  G01R31/317 ,  G06F1/10

摘要： An integrated circuit is provided. The integrated circuit includes a plurality of skitter circuits and a multiplexer that provides the waveform to the plurality of skitter circuits. The plurality of skitter circuits includes at least a first skitter circuit and a second skitter circuit. The first and second skitter circuits are arranged in parallel with respect to an output of the multiplexer. The first skitter circuit can include a first data path and a plurality of first inverters on that first data path. Further, the second skitter circuit can include a second data path, a plurality of second inverters on the second data path, and a delay element connected in series with an input of an initial inverter of the plurality of the second inverters on the second data path.

公开(公告)号：US10608616B2

公开(公告)日：2020-03-31

申请号：US16244002

申请日：2019-01-09

申请人： SOCIONEXT INC.

发明人： Charles Joseph Dedic

IPC分类号： H03K3/017 ,  H03K3/012 ,  H03K5/05 ,  H03K5/135 ,  G06F1/06 ,  G06F1/10 ,  H03K5/01 ,  H03M1/12 ,  H03K5/00 ,  H03M1/66

摘要： Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.