公开(公告)号：US09042191B2

公开(公告)日：2015-05-26

申请号：US13840386

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cormac Michael O'Connell

IPC分类号： G11C7/00 ,  G06F11/10

CPC分类号： G11C29/4401 ,  G06F11/10 ,  G06F11/1064 ,  G11C29/18 ,  G11C29/38

摘要： A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word.

摘要翻译： 存储器阵列具有包括多个存储字的多行。 多个第一比特的每个第一比特与每一行的存储器字相关联。 每个第一位的状态指示相关联的存储器字是否具有错误。 多个冗余行的每个冗余行包括多个冗余字。 每个冗余字与存储器字相关联。 校正数据高速缓存具有至少一个修复字，其被配置为存储校正数据和与至少一个修复字相关联的至少一个状态位，所述状态位指示存储在修复字中的校正数据是否为待修复。 校正数据高速缓存被配置为将存储在修复字中的校正数据写入对应存储器字或对应冗余字中的至少一个。

公开(公告)号：US09041577B2

公开(公告)日：2015-05-26

申请号：US14350698

申请日：2012-10-08

申请人： E2V Semiconductors

发明人： François Bore ,  Marc Wingender ,  Emmanuel Dumaine

IPC分类号： H03M1/66 ,  H03M1/74 ,  H03M1/08

CPC分类号： H03M1/745 ,  H03M1/0863 ,  H03M1/0881

摘要： The invention relates to digital-to-analog converters for converting current. The converter includes a pair of differential branches with two transistors controlled by a digital register activated at a clock frequency, and two resistive loads receiving the currents of the differential branches to produce a differential electrical signal representing the analog result of the conversion. The converter includes a dual switching circuit for the currents of the differential branches: a first switching circuit enables the transmission of the currents of the differential branches toward the loads for 70% to 95% of the clock period and shunts these currents outside the loads for the rest of the time; a second switching circuit alternately and symmetrically makes a direct link followed by a cross link between the differential branches and the loads. The converter provides a signal with high spectral purity and can work with a good level of power in the four Nyquist zones of the spectrum of the output analog signal, and notably in the second and third zones.

摘要翻译： 本发明涉及用于转换电流的数模转换器。 该转换器包括一对具有两个晶体管的差分支路，两个晶体管由数字寄存器控制，数字寄存器以时钟频率激活，两个电阻负载接收差分支路的电流，产生表示转换模拟结果的差分电信号。 转换器包括用于差分分支电流的双重开关电路：第一开关电路使差分支路的电流能够在时钟周期的70％到95％之间向负载传输，并将这些电流分流到负载外部 剩下的时间; 第二开关电路交替对称地形成直接链接，之后是差分分支和负载之间的交叉连接。 该转换器提供具有高光谱纯度的信号，并且可以在输出模拟信号的光谱的四个奈奎斯特区域中，特别是在第二和第三区域中工作，具有良好的功率水平。

公开(公告)号：US09041158B2

公开(公告)日：2015-05-26

申请号：US13403630

申请日：2012-02-23

申请人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yuan-Fu Shao ,  Wen-Huei Guo ,  Tung Ying Lee

发明人： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yuan-Fu Shao ,  Wen-Huei Guo ,  Tung Ying Lee

IPC分类号： H01L29/06 ,  H01L29/02

CPC分类号： H01L29/42368 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/02 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/7856

摘要： A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.

摘要翻译： 半导体装置包括具有受控制的翅片高度的鳍状场效应晶体管（FinFET）。 该装置包括高翅片密度区域和低翅片密度区域。 每个翅片密度区域包括翅片和翅片之间的电介质材料。 电介质材料包括用于不同翅片密度区域的不同掺杂剂浓度，并且是与沉积物相同的材料。

公开(公告)号：US09041078B1

公开(公告)日：2015-05-26

申请号：US14108454

申请日：2013-12-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jam-Wem Lee

IPC分类号： H01L21/66 ,  H01L25/11 ,  H01L25/00

CPC分类号： H01L27/0207 ,  H01L25/11 ,  H01L25/50 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit comprises a first layer and a second layer separate from the first layer. The first layer comprises a power line, a first transistor coupled to the power line, a second transistor coupled to the power line, and a first line coupling the first transistor and the second transistor. The second layer comprises a ground line, a third transistor coupled to the ground line, a fourth transistor coupled to the ground line, and a second line coupling the third transistor and the fourth transistor. The circuit also comprises an inter-layer interconnect that couples the first transistor and the third transistor. The inter-layer interconnect also couples the second transistor and the fourth transistor.

摘要翻译： 电路包括与第一层分开的第一层和第二层。 第一层包括电源线，耦合到电力线的第一晶体管，耦合到电力线的第二晶体管和耦合第一晶体管和第二晶体管的第一线。 第二层包括接地线，耦合到接地线的第三晶体管，耦合到接地线的第四晶体管，以及耦合第三晶体管和第四晶体管的第二线。 电路还包括耦合第一晶体管和第三晶体管的层间互连。 层间互连还耦合第二晶体管和第四晶体管。

公开(公告)号：US09040978B2

公开(公告)日：2015-05-26

申请号：US14463768

申请日：2014-08-20

申请人： Japan Display Inc.

发明人： Toshihiro Sato ,  Masamitsu Furuie

IPC分类号： H01L29/08 ,  H01L51/52 ,  H01L51/00 ,  H01L51/56 ,  H01L51/50

CPC分类号： H01L51/5246 ,  H01L27/3244 ,  H01L27/3276 ,  H01L51/0008 ,  H01L51/5012 ,  H01L51/5206 ,  H01L51/5221 ,  H01L51/5253 ,  H01L51/56 ,  H01L2251/301 ,  H01L2251/566

摘要： A sealing film includes a first inorganic layer that has, in a surface thereof, a convex portion corresponding to an upper surface of an element layer, a second inorganic layer that covers the first inorganic layer, and an organic layer disposed between these layers. The surface of the first inorganic layer includes a recurved area changed from an area around the convex portion to the convex portion, and a flat area surrounding the element layer. The flat area includes an outer peripheral area on an outer end of the first inorganic layer, and an inner peripheral area between the outer peripheral area and the recurved area. The organic layer has an end in the outer peripheral area, has another portion in the recurved area, and avoids the inner peripheral area. A part of the second inorganic layer contacts the first inorganic layer in the inner peripheral area.

摘要翻译： 密封膜包括第一无机层，其表面上具有对应于元件层的上表面的凸部，覆盖第一无机层的第二无机层和设置在这些层之间的有机层。 第一无机层的表面包括从凸部周围的区域向凸部变化的弯曲面，以及围绕元件层的平坦区域。 平坦区域包括在第一无机层的外端上的外周区域和外周区域与反向区域之间的内周区域。 有机层在外周区域中具有端部，在弯曲区域中具有另一部分，并且避免了内周区域。 第二无机层的一部分与内周区域的第一无机层接触。

公开(公告)号：US09040891B2

公开(公告)日：2015-05-26

申请号：US13492348

申请日：2012-06-08

申请人： U-Ting Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Yu-Hao Shih ,  Chih-Chien Wang ,  Shih Pei Chou ,  Wei-Tung Huang ,  Cheng-Ta Wu

发明人： U-Ting Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Yu-Hao Shih ,  Chih-Chien Wang ,  Shih Pei Chou ,  Wei-Tung Huang ,  Cheng-Ta Wu

IPC分类号： H01L27/00 ,  H01L21/033 ,  H01L27/146

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L27/14603 ,  H01L27/1464 ,  H01L27/14689

摘要： A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D1. A mask layer is formed over the substrate. The mask layer has a plurality of openings in the pixel region. A spacer is formed in an interior surface of each opening. A plurality of second trenches is etched through each opening having the spacer in the pixel region. Each of the second trenches has a depth D2. The depth D1 is larger than the depth D2.

摘要翻译： 形成图像传感器装置的方法包括具有像素区域和周边区域的基板。 在周边区域中蚀刻多个第一沟槽。 每个第一沟槽具有深度D1。 掩模层形成在衬底上。 掩模层在像素区域中具有多个开口。 间隔件形成在每个开口的内表面中。 通过在像素区域中具有间隔物的每个开口蚀刻多个第二沟槽。 每个第二沟槽具有深度D2。 深度D1大于深度D2。

公开(公告)号：US09040890B2

公开(公告)日：2015-05-26

申请号：US13427826

申请日：2012-03-22

申请人： Pierre Fereyre ,  Frédéric Mayer

发明人： Pierre Fereyre ,  Frédéric Mayer

IPC分类号： H01L27/148 ,  H01L27/146 ,  H04N5/351 ,  H04N5/3745

CPC分类号： H01L27/14612 ,  H01L27/14603 ,  H04N5/351 ,  H04N5/3745

摘要： This description relates to active-pixel image sensors. Each pixel includes, at the surface of a semiconductor active layer, a photodiode region, a charge storage node and a transfer structure for transferring charges from the photodiode to the storage node after a charge integration time for charges generated by the light in the photodiode. The transfer structure includes a first transfer gate adjacent to the photodiode, a second transfer gate adjacent to the storage node, and an electron-multiplication amplifying structure located between the first and second transfer gates. The amplifying structure includes two separate accelerating gates and an intermediate diode region at a fixed surface potential, located between the two accelerating gates. A succession of alternating high and low potentials is applied to the accelerating gates while the charges are in transit in the transfer structure, before they are transferred to the storage node.

摘要翻译： 该描述涉及有源像素图像传感器。 每个像素在半导体有源层的表面包括光电二极管区域，电荷存储节点和用于在光电二极管中的光产生的电荷的电荷积分时间之后将电荷从光电二极管传输到存储节点的传输结构。 转移结构包括与光电二极管相邻的第一传输门，与存储节点相邻的第二传输门，以及位于第一和第二传输门之间的电子倍增放大结构。 放大结构包括位于两个加速栅极之间的两个单独的加速栅极和处于固定表面电位的中间二极管区域。 交替的高电位和低电位的连续性在转移到存储节点之前，在传输结构中的电荷正在传输期间被应用于加速栅极。

公开(公告)号：US09040393B2

公开(公告)日：2015-05-26

申请号：US13242090

申请日：2011-09-23

申请人： Liang-Gi Yao ,  Chia-Cheng Chen ,  Ta-Ming Kuan ,  Jeff J. Xu ,  Clement Hsingjen Wann

发明人： Liang-Gi Yao ,  Chia-Cheng Chen ,  Ta-Ming Kuan ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/02661 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823418 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes chemically cleaning a surface of a substrate to form a chemical oxide material on the surface. At least a portion of the chemical oxide material is removed at a removing rate of about 2 nanometer/minute (nm/min) or less. Thereafter, a gate dielectric layer is formed over the surface of the substrate.

摘要翻译： 形成半导体器件的方法包括化学清洗衬底的表面以在表面上形成化学氧化物材料。 化学氧化物材料的至少一部分以约2纳米/分钟（nm / min）或更小的去除速率除去。 此后，在衬底的表面上形成栅极电介质层。

公开(公告)号：US09040010B2

公开(公告)日：2015-05-26

申请号：US13267490

申请日：2011-10-06

申请人： Jin-Seok Lee ,  Bo-Yun Jang ,  Young-Soo Ahn

发明人： Jin-Seok Lee ,  Bo-Yun Jang ,  Young-Soo Ahn

IPC分类号： C01B33/02 ,  C30B15/18 ,  C30B15/30 ,  C30B15/10 ,  C30B29/06 ,  C30B35/00

CPC分类号： C30B29/06 ,  C30B15/10 ,  C30B35/002 ,  Y10T117/1032 ,  Y10T117/1068 ,  Y10T117/1072

摘要： The present disclosure provides an apparatus for manufacturing a single crystal silicon ingot having a dual crucible for silicon melting which can be reused due to a dual crucible structure. The apparatus includes a dual crucible for silicon melting, into which raw silicon is charged, a crucible heater heating the dual crucible to melt the raw silicon into molten silicon, a crucible drive unit controlling rotation and elevation of the dual crucible, and a pull-up drive unit disposed above the dual crucible and pulling up a seed crystal dipped in the molten silicon to produce a silicon ingot. The dual crucible has a container shape open at an upper side thereof, and includes a graphite crucible having an inclined surface connecting an inner bottom and an inner wall, and a quartz crucible inserted into the graphite crucible and receiving the raw silicon charged into the dual crucible.

摘要翻译： 本公开提供了一种用于制造具有用于硅熔化的双坩埚的单晶硅锭的装置，其可由于双坩埚结构而被再利用。 该装置包括用于硅熔化的双坩埚，其中加入原料硅，加热双坩埚以将原料硅熔化成熔融硅的坩埚加热器，控制双坩埚旋转和升高的坩埚驱动单元， 设置在双坩埚上方并拉出浸入熔融硅中的晶种以产生硅锭。 双坩埚具有在其上侧开口的容器形状，并且包括具有连接内底和内壁的倾斜表面的石墨坩埚和插入到石墨坩埚中并接收装入双重坩埚的原料硅的石英坩埚 坩。

公开(公告)号：US09038787B1

公开(公告)日：2015-05-26

申请号：US14337573

申请日：2014-07-22

申请人： Adel A. E. Al-Mubarak

发明人： Adel A. E. Al-Mubarak

IPC分类号： B60T1/14 ,  B60T7/12

CPC分类号： B60T1/14 ,  B60T7/12 ,  B60T8/56

摘要： A complementary braking system for removing liquids and solid debris from a motor vehicle's pathway and applying frictional contact in front of two or more of the motor vehicle's tires provide slowing and prevent further movement of the vehicle. The complementary braking system includes a resilient blade disposed forwardly of the motor vehicle's tires and above a road surface. The resilient blade includes an upwardly curved leading edge followed by a generally horizontal flat portion. The system also includes a pair of releasable latches that maintain the resilient blade in an elevated position until released to fall into contact with a road surface The system also includes a pair of electric motors for returning the resilient blade to an elevated latched position above the surface of the road in response to released pressure on the brake pedal.

摘要翻译： 用于从机动车辆的路径移除液体和固体碎屑并在摩托车接触两个或更多的机动车轮胎之前施加摩擦接触的补充制动系统提供减速并防止车辆的进一步移动。 互补制动系统包括设置在机动车辆的轮胎前方和路面上方的弹性叶片。 弹性叶片包括向上弯曲的前缘，后面是大致水平的平坦部分。 该系统还包括一对可释放的闩锁，其将弹性叶片保持在升高的位置，直到释放以与路面接触。该系统还包括一对电动马达，用于将弹性叶片返回到表面上方的升高的闩锁位置 的道路，以响应制动踏板上释放的压力。