公开(公告)号：US10204201B1

公开(公告)日：2019-02-12

申请号：US15199059

申请日：2016-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Lawrence Loh ,  Artur Melo Mota Costa ,  Breno Rodrigues Guimaraes ,  Fabiano Peixoto ,  Andrea Iabrudi Tavares

IPC: G06F17/50

Abstract: Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.

公开(公告)号：US10204180B1

公开(公告)日：2019-02-12

申请号：US14973326

申请日：2015-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Kai-Ti Huang ,  Pinhong Chen ,  Richard M. Chou

IPC: G06F17/50

Abstract: Various embodiments implement an electronic design with automatically generated power intent. One or more inputs to a physical electronic design implementation module may be identified for power intent generation for an electronic design. The power intent for the electronic design may be generated by using at least one or more power related characteristics that are determined from at least the one or more inputs for the power intent generation. With the generated power intent, the electronic design may be implemented at least by guiding the implementation of the electronic design with at least the generated power intent while reducing usage of one or more computing resources.

公开(公告)号：US10198539B1

公开(公告)日：2019-02-05

申请号：US15448436

申请日：2017-03-02

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Tsair-Chin Lin ,  Jingbo Gao ,  Alon Kfir ,  Long Wang ,  Wei Zeng ,  Zhao Li

IPC: G06F17/50

Abstract: Systems, methods, and products implementing a dynamic register transfer level (DRTL) monitor are disclosed. The DRTL monitor may be rapidly constructed and implemented in one or more emulator devices during the runtime of the emulation of a device under test (DUT). The systems may receive monitor modules and corresponding monitor instances in high level hardware description language and compile the monitor modules and instances to generate a monitor within the one or more emulator devices. The systems may then connect one or more input ports of the monitor to one or more signal sources in the DUT. The systems may further allow removal of the monitor, addition or more monitors, and/or modification of the monitor during the run time of the emulation of the DUT.

公开(公告)号：US10198538B1

公开(公告)日：2019-02-05

申请号：US14981270

申请日：2015-12-28

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Barton Quayle ,  Mitchell G. Poplack ,  Sundar Rajan ,  Chuck Berghorn

IPC: G06F17/50 ,  G06F15/173 ,  H03M1/66

Abstract: The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically. The target MUXs may be reprogrammed while emulations are ongoing, in order to redirect data communications between available domains and target pods of target systems.

公开(公告)号：US10193555B1

公开(公告)日：2019-01-29

申请号：US15197324

申请日：2016-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Eric Harris Naviasky ,  Thomas Evan Wilson

IPC: G06F17/50 ,  H03K19/0948 ,  G11C14/00 ,  H03F1/30 ,  G11C11/412 ,  H03K17/687

Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

公开(公告)号：US10192020B1

公开(公告)日：2019-01-29

申请号：US15283081

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/00 ,  G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing dynamic maneuvers within virtual hierarchies of an electronic design. These techniques identify or generate a plurality of figure groups at one or more virtual hierarchies in a layout portion and receive a request to descend into or ascend from a figure group at a virtual hierarchy of the one or more virtual hierarchies. In response to the received request, these techniques update a layout view into an updated layout view at least by exposing layout design details in the figure group for native editing according to the request to descend into or ascend from the figure group and optionally synchronize a corresponding schematic design view according to the updated layout view.

公开(公告)号：US10185795B1

公开(公告)日：2019-01-22

申请号：US15290356

申请日：2016-10-11

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Praveen Ghanta ,  Arun Kumar Mishra

IPC: G06F17/50

Abstract: Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

公开(公告)号：US10180457B1

公开(公告)日：2019-01-15

申请号：US15062013

申请日：2016-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Sharjinder Singh ,  Anil Malik ,  Joseph Michael Swenton

IPC: G01R31/317 ,  G01R31/3177 ,  G06F17/50 ,  G01R31/00 ,  G01R31/311

Abstract: The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.

公开(公告)号：US10176126B1

公开(公告)日：2019-01-08

申请号：US14754508

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Bikram Banerjee ,  Anish Mathew

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/42

Abstract: Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and completion TLPs. PCI implementations may further include an identification-based ordering mechanism to revise the order. The methods identify a completion TLP and multiple posted TLPs, associate a posted TLP with an ordering token, and determine the order for handling the completion and posted TLPs with at least the pointer-based ordering mechanism. The methods may further optionally revise the order with at least the identification-based ordering mechanism.

公开(公告)号：US10176078B1

公开(公告)日：2019-01-08

申请号：US14838709

申请日：2015-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Vincent Motel ,  Andrew Robert Wilmot ,  Tal Tabakman ,  Yonatan Ashkenazi

IPC: G06F11/34 ,  G06F11/36 ,  G06F8/70

Abstract: The present disclosure relates to a system and method for capturing log messages in a post-processing debugging environment. Embodiments may include receiving a processor model associated with an electronic design and generating, using one or more processors and the processor model, a complete view of the state of the memory. Embodiments may further include writing, using one or more processors and the processor model, a log message whenever a designated message logging function is reached within the complete view of the state of the memory.