公开(公告)号：US10103310B2

公开(公告)日：2018-10-16

申请号：US14851536

申请日：2015-09-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Dubois ,  Jean-Francois Robillard ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L35/32 ,  H01L27/16

Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.

公开(公告)号：US10090827B2

公开(公告)日：2018-10-02

申请号：US15414419

申请日：2017-01-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrik Temleitner ,  Fady Abouzeid

IPC: H03K3/356 ,  H03K19/21

Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.

公开(公告)号：US20180277496A1

公开(公告)日：2018-09-27

申请号：US15784883

申请日：2017-10-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Raul Andres Bianchi ,  Benoit Froment

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H03K17/14 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3205 ,  G06F9/44

Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.

公开(公告)号：US20180247874A1

公开(公告)日：2018-08-30

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01C7/12 ,  H01L27/08 ,  H01L49/02 ,  H01L21/74

CPC classification number: H01L21/823493 ,  H01C7/126 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/765 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/8605

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US20180239088A1

公开(公告)日：2018-08-23

申请号：US15692571

申请日：2017-08-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Guerber ,  Charles Baudot ,  Florian Domengie

IPC: G02B6/122 ,  G02B6/26 ,  G02B6/30 ,  G02B6/43 ,  G02B6/138 ,  G02B6/13 ,  G02B6/14

CPC classification number: G02B6/1228 ,  G02B6/12002 ,  G02B6/126 ,  G02B6/13 ,  G02B6/138 ,  G02B6/14 ,  G02B6/262 ,  G02B6/305 ,  G02B6/43

Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.

公开(公告)号：US20180233460A1

公开(公告)日：2018-08-16

申请号：US15788611

申请日：2017-10-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Benoit Froment

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  G01R31/02

CPC classification number: H01L23/573 ,  G01R31/028 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/576 ,  H01L23/642 ,  H01L25/16

Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.

公开(公告)号：US10043837B2

公开(公告)日：2018-08-07

申请号：US15488691

申请日：2017-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/148 ,  H01L27/146

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

公开(公告)号：US20180197781A1

公开(公告)日：2018-07-12

申请号：US15911709

申请日：2018-03-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Gregory Avenier

IPC: H01L21/8228 ,  H01L29/06 ,  H01L27/102 ,  H01L21/311 ,  H01L21/285 ,  H01L21/02 ,  H01L21/265 ,  H01L21/761

CPC classification number: H01L21/82285 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L27/1022 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

公开(公告)号：US10012792B2

公开(公告)日：2018-07-03

申请号：US15217100

申请日：2016-07-22

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Francois Carpentier ,  Patrick Lemaitre ,  Mickael Fourel

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/30 ,  H01L23/13 ,  H01L23/498

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4232 ,  G02B6/4257 ,  G02B6/4269 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/13 ,  H01L23/49827 ,  H01L2224/16225

Abstract: An integrated electronic device includes a substrate having an opening extending therethrough. The substrate includes an interconnection network, and connections coupled to the interconnection network. The connections are to be fixed on a printed circuit board. An integrated photonic module is electrically connected to the substrate, with a portion of the integrated photonic module in front of or overlapping the opening of the substrate. An integrated electronic module is electrically connected to the photonic module, and extends at least partly into the opening of the substrate. The electronic module and the substrate may be electrically connected onto the same face of the photonic module.

公开(公告)号：US20180175022A1

公开(公告)日：2018-06-21

申请号：US15897524

申请日：2018-02-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L27/24 ,  H01L21/84 ,  H01L29/732 ,  H01L45/00 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.