公开(公告)号：US09508604B1

公开(公告)日：2016-11-29

申请号：US15142052

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66803 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins for a type 1 device and a second plurality of fins for a type 2 device, forming a first counter-doped sidewall spacer structure adjacent the first fins, forming a second counter-doped sidewall spacer structure adjacent the second fins and a counter-doped material structure in a space between the first fins, forming a recessed layer of flowable oxide on the devices such that portions of the first and second counter-doped sidewall spacers are exposed above the flowable oxide layer, and performing a common etching process operation to remove at least a portion of the exposed portions of the first and second counter-doped sidewall spacer structures.

Abstract translation: 本文公开的一种说明性方法包括形成用于类型1装置的第一多个翅片和用于2型装置的第二多个翅片，形成与第一翅片相邻的第一反掺杂侧壁间隔结构，形成 邻近第二散热片的第二反掺杂侧壁间隔结构和在第一散热片之间的空间中的反掺杂材料结构，在器件上形成可流动氧化物的凹陷层，使得第一和第二反掺杂侧壁间隔物的部分为 暴露在可流动氧化物层之上，并执行公共蚀刻工艺操作以去除第一和第二反掺杂侧壁间隔结构的暴露部分的至少一部分。

公开(公告)号：US09502308B1

公开(公告)日：2016-11-22

申请号：US14944659

申请日：2015-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L21/70 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/823871 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924

Abstract: A method includes forming first and second contact openings so as to expose first and second source/drain regions, respectively, of a semiconductor material. At least one process operation is performed to selectively form a first liner only in the first contact opening. The first liner covers a bottom portion of the first contact opening and exposes a sidewall portion of the first contact opening. A second liner is formed in the first and second contact openings. At least one process operation is performed so as to form a conductive material above the second liner to fill the first and second contact openings and define first and second contacts conductively coupled to the first and second source/drain regions, respectively.

Abstract translation: 一种方法包括形成第一和第二接触开口以分别暴露半导体材料的第一和第二源/漏区。 执行至少一个处理操作以仅在第一接触开口中选择性地形成第一衬里。 第一衬垫覆盖第一接触开口的底部并暴露第一接触开口的侧壁部分。 第二衬垫形成在第一和第二接触开口中。 执行至少一个处理操作，以在第二衬垫上方形成导电材料，以填充第一和第二接触开口，并分别限定导电耦合到第一和第二源/漏区的第一和第二触点。

公开(公告)号：US09478661B1

公开(公告)日：2016-10-25

申请号：US14696954

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/308 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66795

Abstract: Semiconductor device structures having fin structure(s) and fabrication methods thereof are presented. The methods include: providing a first mask above a substrate structure and a second mask above the first mask and the substrate structure; removing portions of the first mask not underlying the second mask and selectively etching the substrate structure using the second mask to form at least one cavity therein; providing a third mask over portions of the substrate structure not underlying the second mask and removing the second mask; and selectively etching the substrate structure using remaining portions of the first mask and the third mask to the form fin structure(s) of the semiconductor device structure, where the fin structure(s) is self-aligned with the at least one cavity in the substrate structure. For example, the semiconductor device structure can be a fin-type transistor structure, and the method can include forming a source/drain region within a cavity.

Abstract translation: 提出了具有翅片结构的半导体器件结构及其制造方法。 所述方法包括：在第一掩模和衬底结构之上提供衬底结构上方的第一掩模和第二掩模; 去除第一掩模的不在第二掩模下面的部分，并使用第二掩模选择性地蚀刻衬底结构，以在其中形成至少一个空腔; 在不在所述第二掩模下方的所述衬底结构的部分上提供第三掩模并且移除所述第二掩模; 以及使用所述第一掩模和所述第三掩模的剩余部分将所述衬底结构选择性地蚀刻到所述半导体器件结构的形式鳍结构，其中所述鳍结构与所述第一掩模和所述第三掩模中的所述至少一个空腔自对准 底物结构。 例如，半导体器件结构可以是鳍式晶体管结构，并且该方法可以包括在腔内形成源极/漏极区域。

公开(公告)号：US20160181426A1

公开(公告)日：2016-06-23

申请号：US15055805

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion. First and second contact trenches extend continuously along the first gate structure portion for less than the axial length of the gate structure and are positioned above at least a portion of the active region on respective opposing first and second sides of the gate structure. An epi semiconductor material is positioned on the active region within each of the first and second contact trenches.

Abstract translation: 一种器件包括具有位于半导体衬底的有源区上方的轴向长度的栅极结构，并且包括位于有源区上方的第一栅极结构部分和位于半导体衬底中形成的隔离区上方的第二栅极结构部分。 蚀刻停止层位于栅极结构上并且覆盖第二栅极结构部分的侧壁表面，但不覆盖第一栅极结构部分的任何侧壁表面。 第一和第二接触沟槽沿着第一栅极结构部分连续延伸以小于栅极结构的轴向长度，并且位于栅极结构的相对的相对的第一和第二侧上的有源区域的至少一部分上方。 外延半导体材料位于第一和第二接触沟槽的每一个内的有源区域上。

公开(公告)号：US20160133716A1

公开(公告)日：2016-05-12

申请号：US14995956

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

公开(公告)号：US20160056253A1

公开(公告)日：2016-02-25

申请号：US14467357

申请日：2014-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Rohit Galatage ,  Hoon Kim

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L29/78 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/283 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517

Abstract: Integrated circuits with a diffusion barrier layers, and processes for preparing integrated circuits including diffusion barrier layers are provided herein. An exemplary integrated circuit includes a semiconductor substrate comprising a semiconductor material, a compound gate dielectric overlying the semiconductor substrate, and a gate electrode overlying the compound gate dielectric. In this embodiment, the compound gate dielectric includes a first dielectric layer, a diffusion barrier layer overlying the first dielectric layer; and a second dielectric layer overlying the diffusion barrier layer; wherein the diffusion barrier layer is made of a material that is less susceptible to diffusion of the semiconductor material than the first dielectric layer, less susceptible to diffusion of oxygen than the second dielectric layer, or both.

Abstract translation: 具有扩散阻挡层的集成电路，以及用于制备包括扩散阻挡层的集成电路的方法。 示例性集成电路包括半导体衬底，其包括半导体材料，覆盖半导体衬底的复合栅极电介质和覆盖复合栅极电介质的栅电极。 在该实施例中，复合栅极电介质包括第一介电层，覆盖第一介电层的扩散阻挡层; 以及覆盖所述扩散阻挡层的第二电介质层; 其中所述扩散阻挡层由比所述第一电介质层更不易受半导体材料扩散影响的材料制成，不如第二电介质层易受氧扩散的影响，或两者兼而有之。

公开(公告)号：US20160042954A1

公开(公告)日：2016-02-11

申请号：US14452606

申请日：2014-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/28123 ,  H01L21/28088 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.

Abstract translation: 本发明的实施例提供了一种替代金属栅极和具有减小的光刻步骤的制造工艺。 使用选择性蚀刻技术，使用一层填充金属来保护沟槽中的电介质层，消除了对一些光刻步骤的需要。 这又降低了整体成本和制造的复杂性。 此外，在蚀刻期间提供额外的保护，其用于提高产品产率。

公开(公告)号：US09236299B2

公开(公告)日：2016-01-12

申请号：US14201255

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Christian Witt ,  Larry Zhao

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76882 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

Abstract translation: 一种方法包括在绝缘材料的沟槽/开口中形成阻挡层，在阻挡层之上形成铜材料的第一区域，在铜材料的第一区域上的沟槽/开口中形成金属层，形成第二层 在金属层上的铜材料区域，执行至少一个CMP工艺以去除位于沟槽/开口外部的绝缘材料层的平坦化上表面上方的任何材料，从而限定由金属层定位的结构 在铜材料的第一和第二区域之间，在绝缘材料层之上并在结构之上形成电介质盖层，并进行金属扩散退火工艺以形成至少与导电铜结构的上表面相邻的金属盖层 。

公开(公告)号：US09178036B1

公开(公告)日：2015-11-03

申请号：US14492629

申请日：2014-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Naim Moumen ,  Chanro Park ,  Hoon Kim ,  Steven Bentley

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/092 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one recess etching process such that a first portion of a high-k oxide gate insulation layer and a first portion of a metal oxide layer is positioned entirely within a first gate cavity and a second portion of the high-k oxide gate insulation layer, a conformal patterned masking layer and a second portion of the metal oxide layer is positioned entirely within a second gate cavity, performing at least one heating process to form a composite metal-high-k oxide alloy gate insulation layer in the first gate cavity, while preventing metal from the metal oxide material from being driven into the second portion of the high-k oxide gate insulation layer in the second gate cavity during the at least one heating process, and forming gate electrode structures in the gate cavities.

Abstract translation: 本文公开的一种说明性方法包括进行至少一个凹陷蚀刻工艺，使得高k氧化物栅极绝缘层的第一部分和金属氧化物层的第一部分完全位于第一栅极腔内， 高k氧化物栅极绝缘层的第二部分，共形图案化掩模层和金属氧化物层的第二部分完全位于第二栅极腔内，执行至少一个加热工艺以形成复合金属 - k氧化物合金栅极绝缘层，同时防止来自金属氧化物材料的金属在至少一个加热过程中被驱入第二栅极腔中的高k氧化物栅极绝缘层的第二部分，以及 在门腔中形成栅电极结构。

公开(公告)号：US20150311308A1

公开(公告)日：2015-10-29

申请号：US14261559

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shariq Siddiqui ,  Bhagawan Sahu ,  Rohit Galatage ,  Hoon Kim

IPC: H01L29/51 ,  H01L21/02

CPC classification number: H01L29/513 ,  H01L21/28255 ,  H01L29/517

Abstract: Embodiments of the present invention provide a high-K dielectric film for use with silicon germanium (SiGe) or germanium channel materials, and methods of fabrication. As a first step of this process, an interfacial layer (IL) is formed on the semiconductor substrate providing reduced interface trap density. However, an ultra-thin layer is used as a barrier film to avoid germanium diffusion in high-k film and oxygen diffusion from the high-k film to the interfacial layer (IL), therefore, dielectric films such as aluminum oxide (Al2O3), zirconium oxide, or lanthanum oxide (La2O3) may be used. In addition, these films can provide high thermal budget. A second dielectric layer is then deposited on the first dielectric layer. The second dielectric layer is a high-k dielectric layer, providing a reduced effective oxide thickness (EOT), resulting in improved device performance.

Abstract translation: 本发明的实施方案提供了用于硅锗（SiGe）或锗通道材料的高K电介质膜及其制造方法。 作为该方法的第一步，在半导体衬底上形成界面层（IL），提供降低的界面陷阱密度。 然而，使用超薄层作为阻挡膜，以避免高k膜中的锗扩散和从高k膜到界面层（IL）的氧扩散，因此，诸如氧化铝（Al 2 O 3）的介电膜， ，氧化锆或氧化镧（La 2 O 3）。 此外，这些电影可以提供高热预算。 然后在第一介电层上沉积第二介电层。 第二电介质层是高k电介质层，提供有效的氧化物厚度（EOT）降低，从而提高器件性能。