公开(公告)号：US09793372B1

公开(公告)日：2017-10-17

申请号：US15163806

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.

公开(公告)号：US09735174B2

公开(公告)日：2017-08-15

申请号：US14596331

申请日：2015-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/265 ,  H01L21/285 ,  H01L21/84 ,  H01L27/108 ,  H01L49/02 ,  H01L29/06 ,  H01L29/786 ,  H01L27/06 ,  H01L29/94

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10829 ,  H01L27/1085 ,  H01L27/1087 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/786 ,  H01L29/94

Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.

公开(公告)号：US09620589B2

公开(公告)日：2017-04-11

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

公开(公告)号：US09583240B2

公开(公告)日：2017-02-28

申请号：US14469012

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01C7/10 ,  H01C1/16 ,  H01C7/02 ,  H01C7/04 ,  H01C7/00 ,  H01C17/075

CPC classification number: H01C1/16 ,  H01C7/008 ,  H01C7/021 ,  H01C7/027 ,  H01C7/041 ,  H01C17/075

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract translation: 本公开内容涉及包括正温度系数热敏电阻和负温度系数热敏电阻的半导体结构，该正温度系数热敏电阻和负温度系数热敏电阻通过连接元件彼此并联连接，连接元件被构造成使得由并联连接产生的电阻在预定的 温度范围和相应的制造方法。

公开(公告)号：US20170040354A1

公开(公告)日：2017-02-09

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12 ,  H01L49/02 ,  H01L29/66

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract translation: 根据一些示例性实施例，本公开提供包括形成在半导体衬底中的有源区的电容器结构，包括形成在有源区中的源区和漏区以及形成在有源区上方的栅极的MOSFET器件，以及 第一电极和形成在MOSFET器件上方的金属化层中的第二电极，其中第一电极经由相应的源极和漏极触点与源极和漏极区域电连接，并且第二电极经由栅极触点与栅电极电连接 。

公开(公告)号：US20170025398A1

公开(公告)日：2017-01-26

申请号：US14803466

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.

Abstract translation: 半导体管芯设置有被配置为将光信号传输到另一管芯的光发射器和被配置为从另一管芯接收光信号的光接收器。 此外，提供一种形成半导体器件的方法，包括以下步骤形成第一半导体管芯：提供半导体衬底，至少部分地在半导体衬底上形成晶体管器件，形成光接收器，至少部分地覆盖 至少部分地在所述半导体衬底中，在所述晶体管器件上形成金属化层，以及至少部分地在所述金属化层上并且至少部分地在所述金属化层中形成光发射器。

公开(公告)号：US09490189B2

公开(公告)日：2016-11-08

申请号：US14270941

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L23/38 ,  H01L35/32 ,  G06F1/20 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L23/38 ,  G06F1/20 ,  H01L25/0652 ,  H01L25/162 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Abstract translation: 公开了一种控制包括层叠器件配置的半导体器件中的温度的方法。 该方法包括提供一种珀尔帖元件，其具有形成在层叠器件配置的第一衬底之上的金属基散热器和形成在堆叠器件配置的第二衬底之上的金属基热源，并且建立通过珀尔帖的电流 当半导体器件处于指定的工作阶段时。

公开(公告)号：US20160307926A1

公开(公告)日：2016-10-20

申请号：US15193770

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

Abstract translation: 公开了一种集成电路产品，其包括SOI结构，其包括体半导体衬底，位于体半导体衬底上的掩埋绝缘层和位于绝缘层上的半导体层，其中在SOI结构的第一区域中，半导体层 并且去除了掩埋绝缘层，并且在SOI结构的第二区域中，半导体层和掩埋绝缘层存在于体半导体衬底之上。 该产品还包括半导体本体器件，其包括位于第一区域中的体半导体衬底上的第一栅极结构和包括位于第二区域中的半导体层上的第二栅极结构的SOI半导体器件，其中第一和第二栅极结构 具有基本上延伸到体半导体衬底的上表面上方的共同高度水平的最终栅极高度。

公开(公告)号：US09466717B1

公开(公告)日：2016-10-11

申请号：US14680172

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/82 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.

Abstract translation: 本公开在第一方面提供了一种半导体器件，其包括SOI衬底部分，形成在SOI衬底部分上的栅极结构以及具有各自的源极和漏极高度水平的源极和漏极区域，其中源极和漏极高度水平是不同的 。 可以通过在SOI衬底部分上形成栅极结构来形成半导体器件，在栅极结构的一侧凹入SOI衬底部分，以形成与栅极结构相邻的沟槽，并在栅极结构的相对侧形成源极和漏极区域 栅极结构，其中一个源极和漏极区域形成在沟槽中。

公开(公告)号：US20160268426A1

公开(公告)日：2016-09-15

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract translation: 半导体器件包括多个间隔开的翅片，位于多个间隔开的翅片中的每一个之间的介电材料层，以及位于电介质材料层上方并延伸穿过翅片的公共栅极结构。 连续合并的半导体材料区域位于每个散热片上并且位于电介质材料层上方，与公共栅极结构横向间隔开，在翅片之间延伸并物理接触翅片，具有面向公共栅极结构的第一侧壁表面 并且具有与第一侧壁表面相对并且远离公共栅极结构的第二侧壁表面。 应力诱导材料定位在由至少第一侧壁表面，相邻的一对翅片的相对侧壁表面和介电材料层的上表面限定的空间中。