公开(公告)号：US20250008680A1

公开(公告)日：2025-01-02

申请号：US18344638

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Min Suet Lim ,  Lance Lin ,  Arnab Sen ,  Jiacheng Wu

IPC: H05K7/20 ,  G06F1/20

Abstract: Thermal management systems for electronic devices and related methods are disclosed. An example electronic device includes a chassis including a first cover and a second cover, the first cover including an upper surface and a plurality of side walls and the second cover including a lower surface of the chassis, the first cover and the second cover defining an internal cavity of the chassis, the first cover including a first device inlet formed in a first side wall of the first cover; a fan positioned in the internal cavity, the fan including a first fan inlet and a second fan inlet opposite the first fan inlet; and a side channel positioned between the first device inlet and the first fan inlet to direct fluid flow between the first device inlet and the first fan inlet.

公开(公告)号：US20240397662A1

公开(公告)日：2024-11-28

申请号：US18200994

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Mark McDonald ,  Min Suet Lim ,  Tongyan Zhai ,  Shantanu D. Kulkarni ,  Arnab A. Sen ,  Juha Paavola

IPC: H05K7/20 ,  H05K5/02

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for accessories for electronic devices and removable fan cartridges for electronic devices. An example electronic device accessory includes a backplate panel removably couplable to a first chassis of a first electronic device to replace a portion of a first cover of the first chassis and removably couplable to a second chassis of a second electronic device to replace a portion of a second cover of the second chassis. The example electronic device accessory also includes a mating device to releasably couple the backplate panel to the first chassis and independently releasably couple the backplate panel to the second chassis and a fan coupled to the backplate panel. The fan is to increase a Z height of the first electronic device when the backplate panel is coupled to the first electronic device and increase a Z height of the second electronic device when the backplate panel is coupled to the second electronic device.

公开(公告)号：US20240234234A9

公开(公告)日：2024-07-11

申请号：US17972923

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20240136279A1

公开(公告)日：2024-04-25

申请号：US17972975

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

公开(公告)号：US20240136243A1

公开(公告)日：2024-04-25

申请号：US17972923

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Ilan Ronen ,  Kavitha Nagarajan ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/532

CPC classification number: H01L23/367 ,  H01L23/42 ,  H01L23/53233

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

公开(公告)号：US20230385507A1

公开(公告)日：2023-11-30

申请号：US18326772

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Adam Norman ,  Min Suet Lim ,  Miaomiao Ma ,  Mackenzie Norman ,  John Vu ,  Ching Leong Ooi ,  Eng Same Tan ,  Luis Carlos Alvarez Mata

IPC: G06F30/392 ,  G06F30/27

CPC classification number: G06F30/392 ,  G06F30/27

Abstract: Systems, apparatuses and methods may provide for technology that receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area, aggregates the parameter results and scores, and generates a global placement model based on an output of the aggregated parameter results and scores.

公开(公告)号：US11823994B2

公开(公告)日：2023-11-21

申请号：US17671478

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/31 ,  H01L23/49866 ,  H01L23/50 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

公开(公告)号：US11710029B2

公开(公告)日：2023-07-25

申请号：US16147037

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kooi Chi Ooi ,  Min Suet Lim ,  Denica Larsen ,  Lady Nataly Pinilla Pico ,  Divya Vijayaraghavan

IPC: G06N3/045 ,  G06N3/08 ,  G06N5/04 ,  G06N3/063 ,  G06F15/78 ,  G06F1/16 ,  G06N20/00 ,  G06F16/00 ,  G06N3/084 ,  G06V10/94 ,  G06F18/214 ,  G06F18/21 ,  G06F18/2413 ,  G06N3/048 ,  G06V10/764 ,  G06V10/774 ,  G06V10/776 ,  G06V10/82

CPC classification number: G06N3/063 ,  G06F1/163 ,  G06F15/7892 ,  G06F16/00 ,  G06F18/214 ,  G06F18/217 ,  G06F18/24143 ,  G06N3/045 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084 ,  G06N5/04 ,  G06N20/00 ,  G06V10/764 ,  G06V10/774 ,  G06V10/776 ,  G06V10/82 ,  G06V10/955

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.

公开(公告)号：US11696409B2

公开(公告)日：2023-07-04

申请号：US16325659

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Min Suet Lim ,  Hoay Tien Teoh ,  Mooi Ling Chang ,  Chin Lee Kuan

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/16

CPC classification number: H05K1/184 ,  H05K1/111 ,  H05K1/113 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/183 ,  H05K2201/0305 ,  H05K2201/09072 ,  H05K2201/10454

Abstract: A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

公开(公告)号：US11664317B2

公开(公告)日：2023-05-30

申请号：US17024263

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Eng Huat Goh ,  MD Altaf Hossain

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/31 ,  H01L23/50 ,  H01L23/498 ,  H01L25/065 ,  H01L49/02 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/565 ,  H01L23/31 ,  H01L23/5223 ,  H01L23/5385 ,  H01L23/5386 ,  H01L28/40

Abstract: Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.