公开(公告)号：US09608067B2

公开(公告)日：2017-03-28

申请号：US14672311

申请日：2015-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Hong He ,  Juntao Li

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/28 ,  H01L29/161

CPC classification number: H01L29/1054 ,  H01L21/28026 ,  H01L21/28158 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

公开(公告)号：US20170069492A1

公开(公告)日：2017-03-09

申请号：US14847619

申请日：2015-09-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Juntao Li

IPC: H01L21/02 ,  G01N33/00 ,  H01L29/06 ,  H01L29/161 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/02694 ,  B82Y15/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01N33/0036 ,  G01N33/005 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02606 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  Y10S977/814 ,  Y10S977/89 ,  Y10S977/90 ,  Y10S977/957

Abstract: Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

Abstract translation: 提供了形成纳米结构材料的技术。 在本发明的一个方面，一种用于在埋层绝缘体上形成纳米管的方法包括以下步骤：在SOI晶片的SOI层中形成一个或多个翅片，其中SOI晶片具有通过埋置的SOI层与SOI层分离的衬底 绝缘子; 在翅片上形成SiGe层; 在足以从SiGe层驱入Ge到翅片中的条件下退火SiGe层，并形成完全围绕每个翅片的SiGe壳; 并且去除对SiGe壳体有选择性的散热片，其中剩余的SiGe壳体在埋入的绝缘体上形成纳米管。 还提供了纳米管结构和形成纳米管器件的方法。

公开(公告)号：US20170040437A1

公开(公告)日：2017-02-09

申请号：US15298828

申请日：2016-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

Abstract translation: 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US20170033219A1

公开(公告)日：2017-02-02

申请号：US14949977

申请日：2015-11-24

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Effendi Leobandung ,  Gen Tsutsui ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.

Abstract translation: finFET半导体器件包括在衬底的上表面上的至少一个半导体鳍片。 半导体鳍片包括介于相对的源极/漏极区域之间的沟道区域。 栅极堆叠在衬底的上表面上，并且仅包围沟道区域的侧壁和上表面。 沟道区域还包括由第一半导体材料和第二半导体材料形成的聚集部分。 源极/漏极区域由第一半导体材料形成，同时排除第二半导体材料。

公开(公告)号：US09543407B2

公开(公告)日：2017-01-10

申请号：US14191751

申请日：2014-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

Abstract translation: 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。

公开(公告)号：US09515185B2

公开(公告)日：2016-12-06

申请号：US14588116

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Hong He ,  Bruce Doris

IPC: H01L27/01 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L27/12

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract translation: 结构稳定的绝缘体上的FinFET采用氮化硅衬垫以防止SiGe鳍底部的稳定化氧化。 氮化硅衬垫阻止氧气进入翅片的下角，以便制造高浓度SiGe翅片。 氮化硅衬垫即使其厚度小于约5nm也是有效的。 使用SiN衬垫为具有较高锗含量，在25-55％锗浓度范围内的翅片提供结构稳定性。

公开(公告)号：US20160343621A1

公开(公告)日：2016-11-24

申请号：US15229754

申请日：2016-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li ,  Junli Wang

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L29/161 ,  H01L29/16 ,  H01L29/20 ,  H01L21/84 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.

Abstract translation: 形成从半导体衬底的剩余部分向上延伸的半导体芯棒结构。 第一氧化物隔离结构形成在半导体衬底的剩余部分的暴露表面和每个半导体芯棒结构之间。 在每个半导体芯棒结构的相对的侧壁上形成硅锗合金翅片，其存在于半导体衬底的pFET器件区域中并且直接位于每个第一氧化物隔离结构的表面上。 去除每个半导体芯棒结构，并且在每个第一氧化物隔离结构之间形成第二氧化物隔离结构，并延伸到每个第一氧化物隔离结构的最下表面之下。

公开(公告)号：US09484440B2

公开(公告)日：2016-11-01

申请号：US14752095

申请日：2015-06-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract translation: 具有非合并翅片延伸的半导体器件及其形成方法。 用于形成半导体器件的方法包括在衬底上形成翅片; 在翅片上形成虚拟栅极，留下源极和漏极区域; 在低于周围绝缘体层的表面水平面处蚀刻散热片; 并从蚀刻的翅片外延生长翅片延伸部分。

公开(公告)号：US20160300721A1

公开(公告)日：2016-10-13

申请号：US15182995

申请日：2016-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US09431425B1

公开(公告)日：2016-08-30

申请号：US14674586

申请日：2015-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li ,  Junli Wang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L29/161 ,  H01L29/06 ,  H01L21/762 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.

Abstract translation: 形成从半导体衬底的剩余部分向上延伸的半导体芯棒结构。 第一氧化物隔离结构形成在半导体衬底的剩余部分的暴露表面和每个半导体芯棒结构之间。 在每个半导体芯棒结构的相对的侧壁上形成硅锗合金翅片，其存在于半导体衬底的pFET器件区域中并且直接位于每个第一氧化物隔离结构的表面上。 去除每个半导体芯棒结构，并且在每个第一氧化物隔离结构之间形成第二氧化物隔离结构，并延伸到每个第一氧化物隔离结构的最下表面之下。