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公开(公告)号：US09001590B2
公开(公告)日：2015-04-07
申请号：US13710529
申请日：2012-12-11
Applicant: Macronix International Co., Ltd.
Inventor： Hang-Ting Lue
IPC: G11C16/04 , G11C16/06 , G11C16/34 , H01L29/792 , H01L27/115 , G11C16/14
CPC classification number: G11C16/04 , G11C16/0416 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/349 , H01L27/1157 , H01L29/792
Abstract: A method for operating a semiconductor structure is provided. The semiconductor structure includes a first conductor extending in a first direction, a second conductor extending in a second direction different from the first direction, and a dielectric layer between the first conductor and the second conductor. The method for operating the semiconductor structure comprises following steps. A current is provided to flow in the first direction in the first conductor.
Abstract translation: 提供了一种用于操作半导体结构的方法。 半导体结构包括沿第一方向延伸的第一导体，在与第一方向不同的第二方向上延伸的第二导体，以及在第一导体和第二导体之间的介电层。 用于操作半导体结构的方法包括以下步骤。 提供电流以在第一导体中沿第一方向流动。
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公开(公告)号：US20140211563A1
公开(公告)日：2014-07-31
申请号：US13940010
申请日：2013-07-11
Applicant: Macronix International Co., Ltd.
Inventor： Kuo-Pin Chang , Wen-Wei Yeh , Chih-Shen Chang , Hang-Ting Lue
IPC: G11C16/34
CPC classification number: G11C16/3459 , G11C16/3427
Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.
Abstract translation: 描述了一种存储器件，其包括具有由多个字线访问的多个级别的存储器单元的存储器单元的三维阵列以及多个位线。 控制电路耦合到多个字线和多个位线。 控制电路适用于通过热载流子生成辅助FN隧道在阵列的选定电平和所选择的字线上对选定的存储单元进行编程，同时抑制未选择的电平和所选电平中的未选定存储单元的干扰 未经选择的字线通过自我提升。
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公开(公告)号：US08760928B2
公开(公告)日：2014-06-24
申请号：US13710992
申请日：2012-12-11
Applicant: Macronix International Co., Ltd
Inventor： Ti-Wen Chen , Hang-Ting Lue , Shuo-Nan Hung , Shih-Lin Huang , Chih-Chang Hsieh , Kuo-Pin Chang
CPC classification number: G11C16/26 , G11C5/146 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/24 , H01L27/11524 , H01L27/1157
Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.
Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。
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124.发明申请公开(公告)号：US20130270626A1
公开(公告)日：2013-10-17
申请号：US13913176
申请日：2013-06-07
Applicant: Macronix International Co., Ltd.
Inventor： Hang-Ting Lue
IPC: H01L29/792
CPC classification number: G11C5/06 , G11C5/02 , H01L27/0688 , H01L27/101 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L2924/0002 , H01L2924/00
Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.
Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 导线符合堆叠的表面。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。 存储器元件是可编程的，如抗熔丝或电荷捕获结构。 3D存储器仅使用两层用于多层的关键掩模。
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公开(公告)号：US20130161835A1
公开(公告)日：2013-06-27
申请号：US13772121
申请日：2013-02-20
Applicant: Macronix International Co., Ltd.
Inventor： Shih-Hung Chen , Hang-Ting Lue , Hong-Ji Lee , Chin-Cheng Yang
IPC: H01L23/50
CPC classification number: H01L23/50 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76838 , H01L23/481 , H01L23/522 , H01L23/5226 , H01L24/19 , H01L27/0207 , H01L27/0688 , H01L27/11206 , H01L27/11286 , H01L27/11565 , H01L27/11578 , H01L27/11582 , H01L2924/1306 , H01L2924/14 , H01L2924/00
Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.
Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。
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Patent Agency Ranking
公开(公告)号：US12245428B2
公开(公告)日：2025-03-04
申请号：US17575418
申请日：2022-01-13
Applicant: MACRONIX International Co., Ltd.
Inventor： Hang-Ting Lue , Chia-Jung Chiu , Teng-Hao Yeh , Guan-Ru Lee
IPC: H10B41/27 , H10B41/10 , H10B43/10 , H10B43/27 , H01L21/786
Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.
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公开(公告)号：US12245413B2
公开(公告)日：2025-03-04
申请号：US17695943
申请日：2022-03-16
Applicant: Macronix International Co., Ltd.
Inventor： Hang-Ting Lue , Wei-Chen Chen , Teng-Hao Yeh
Abstract: Methods, devices, systems, and apparatus for three-dimensional semiconductor structures are provided. In one aspect, a semiconductor device includes: a semiconductor substrate, multiple conductive layers vertically stacked on the semiconductor substrate, and multiple transistors. The multiple conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer that are sequentially stacked together. The multiple transistors include a first transistor and a second transistor in the first conductive layer and a third transistor in the third conductive layer. Each transistor includes a first terminal, a second terminal, and a gate terminal. First terminals of the first, second, and third transistors are conductively coupled to a first conductive node in the second conductive layer.
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公开(公告)号：US12224034B2
公开(公告)日：2025-02-11
申请号：US18311800
申请日：2023-05-03
Applicant: MACRONIX International Co., Ltd.
Inventor： Chih-Chang Hsieh , Hang-Ting Lue
Abstract: A memory device and a data approximation search method thereof are proposed. The memory device includes a plurality of selection switch pairs, a plurality of memory cell string pairs, a sense amplifier, and a page buffer. The selection switch pairs receive multiple search data pairs, respectively. The memory cell string pairs are respectively coupled to a global bit line through the selection switch pairs. Each of the memory cell string pairs determines whether to provide current on the global bit line according to stored data of a selected memory cell pair and each of the search data pairs. The sense amplifier obtains multiple search results according to the current on the global bit line and at least one reference currents respectively corresponding to at least one similarity. The page buffer records the search results and generates similarity information by accumulating the search results.
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公开(公告)号：US20240407151A1
公开(公告)日：2024-12-05
申请号：US18636270
申请日：2024-04-16
Applicant: MACRONIX International Co., Ltd.
Inventor： Wei-Chen Chen , Hang-Ting Lue
Abstract: A memory cell circuit, a memory cell array structure and a manufacturing method thereof are provided. The memory cell circuit includes a first transistor, a second transistor and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to a second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. A first end of the capacitor is electrically coupled to a second end of the second transistor and a second end of the capacitor receives a reference voltage.
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公开(公告)号：US12094518B2
公开(公告)日：2024-09-17
申请号：US17988760
申请日：2022-11-17
Applicant: MACRONIX International Co., Ltd.
Inventor： Teng-Hao Yeh , Hang-Ting Lue , Chih-Wei Hu
IPC: G11C11/40 , G11C11/4074 , G11C11/408
CPC classification number: G11C11/4085 , G11C11/4074 , G11C11/4087
Abstract: A memory device, such as three dimension AND Flash memory, including a plurality of word line decoding circuit areas, a plurality of common power rails and a plurality of power drivers is provided. The word line decoding circuit areas are arranged in an array, and form a plurality of isolation areas, wherein each of the isolation areas is disposed between two adjacent word line decoding circuit areas. Each of the common power rails is disposed along the isolation areas. The power drivers respectively correspond to the word line decoding circuit areas. Each of the power drivers is disposed between each of the power driving circuit areas and each of the corresponding isolation areas, wherein each of the power drivers is configured to provide a common power to the word line decoding circuit areas.
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