Multiple patterning method
    122.
    发明授权
    Multiple patterning method 有权
    多重图案化方法

    公开(公告)号:US08941166B2

    公开(公告)日:2015-01-27

    申请号:US12981121

    申请日:2010-12-29

    摘要: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

    摘要翻译: 集成电路存储器包括一组线,每条线在第一区域中具有平行的X方向线部分,在第二区域具有Y方向线部分。 第二区域偏离第一区域。 X方向线部分的长度比Y方向线部分的长度大得多。 X方向和Y方向线部分具有相应的第一和第二间距,其中第二间距比第一间距大至少3倍。 触点拾取区域在Y方向线部分。 在一些示例中,这些线包括字线或位线。 可以使用多个图案化方法来创建记忆,以产生材料线,然后平行的X方向线部分和平行的Y方向线部分。

    Structure of ECC spare bits in 3D memory
    123.
    发明授权
    Structure of ECC spare bits in 3D memory 有权
    3D存储器中ECC备用位的结构

    公开(公告)号:US08935594B2

    公开(公告)日:2015-01-13

    申请号:US13052762

    申请日:2011-03-21

    摘要: A structure of 3D memory comprises a plurality of stacking layers and a plurality of cells. The stacking layers are arranged in a three-dimensional array and disposed parallel to each other on a substrate, and the stacking layers comprises a plurality of stacking memory layers. The cells comprises a first group of cells (such as m of cells) for storing information data and a second group of cells (such as n of cells) for storing ECC (error checking and correcting) spare bits. All of the first group and the second group of cells are read out at the same time for performing an ECC function. The ECC spare bits in the 3D memory according to the present disclosure can be constructed at the same physical layer or at the different physical layers. The embodiments can be implemented, but not limited, by a vertical-gate (VG) structure or a finger VG structure.

    摘要翻译: 3D存储器的结构包括多个堆叠层和多个单元。 堆叠层被布置成三维阵列并且在衬底上彼此平行地布置,并且层叠层包括多个层叠存储层。 这些单元包括用于存储信息数据的第一组单元(例如,单元格m)和用于存储ECC(错误检查和校正)备用位的第二组单元(例如n个单元)。 同时读出所有第一组和第二组单元,以执行ECC功能。 根据本公开的3D存储器中的ECC备用位可以在相同的物理层或不同的物理层构造。 实施例可以通过垂直门(VG)结构或手指VG结构来实现但不限于此。

    Mask Design With Optically Isolated Via and Proximity Correction Features
    125.
    发明申请
    Mask Design With Optically Isolated Via and Proximity Correction Features 有权
    具有光学隔离通孔和接近校正功能的面膜设计

    公开(公告)号:US20140078804A1

    公开(公告)日:2014-03-20

    申请号:US13619124

    申请日:2012-09-14

    IPC分类号: G11C5/06 G03F1/38 G06F17/50

    摘要: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.

    摘要翻译: 一种光刻掩模和用于制造这种掩模的方法,其包括光学隔离的特征和接近校正特征。 包括定义通孔的通孔特征的通孔图案以掩模上每行和列之间的行和列间距的行和列定位在掩模上。 通孔图案被定位成使得相邻列中的通孔特征由它们之间的至少一个中间行分开。 通孔图案也可以被定位成使得相邻行中的通孔图案被它们之间的至少一个中间柱隔开。 结果,每个通孔图案的通孔特征和位于每个通孔特征周围的相关联的光学邻近校正特征不与周围通孔图案的光学邻近校正特征和通孔特征重叠。

    Integrated Circuit Connector Access Region and Method for Making
    126.
    发明申请
    Integrated Circuit Connector Access Region and Method for Making 有权
    集成电路连接器接入区域及制造方法

    公开(公告)号:US20140054784A1

    公开(公告)日:2014-02-27

    申请号:US13594372

    申请日:2012-08-24

    申请人: Shih-Hung Chen

    发明人: Shih-Hung Chen

    IPC分类号: H01L21/768 H01L23/535

    摘要: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

    摘要翻译: 集成电路器件的连接器接入区域包括沿第一方向延伸的一组平行导体和层间连接器。 导体包括在不同导体上的一组导电接触区域,其限定了在接触平面下方延伸的导体的接触平面。 一组接触区域以相对于第一方向的倾斜角度(例如小于45°或5°至27°)限定一条线。 层间连接器与接触区域电接触并在接触面上方延伸。 层间连接器中的至少一些覆盖在电绝缘体上,并与电接触部分相邻的电导体隔离。 该组平行导体可以包括一组导电层,其中接触平面大致垂直于导电层。

    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE
    127.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
    具有改进位线电容的半导体结构

    公开(公告)号:US20140054535A1

    公开(公告)日:2014-02-27

    申请号:US13594353

    申请日:2012-08-24

    IPC分类号: H01L47/00

    摘要: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译: 具有改善的位线电容的半导体结构包括衬底,堆叠存储器结构,多个位线,第一阶梯接触结构,第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上,并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中,其中位线通过,然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

    Integrated Circuit Capacitor and Method
    128.
    发明申请
    Integrated Circuit Capacitor and Method 有权
    集成电路电容器和方法

    公开(公告)号:US20130277799A1

    公开(公告)日:2013-10-24

    申请号:US13451428

    申请日:2012-04-19

    IPC分类号: H01L29/92 H01L21/02

    CPC分类号: H01L28/91

    摘要: An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

    摘要翻译: 电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。 一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。 电导体从互连区域电连接到电极层,用于进入电容器组件的电极层。

    Stacked IC device with recessed conductive layers adjacent to interlevel conductors
    129.
    发明授权
    Stacked IC device with recessed conductive layers adjacent to interlevel conductors 有权
    具有与层间导体相邻的凹陷导电层的堆叠IC器件

    公开(公告)号:US08541882B2

    公开(公告)日:2013-09-24

    申请号:US13240058

    申请日:2011-09-22

    IPC分类号: H01L23/48 H01L21/283

    摘要: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

    摘要翻译: IC器件包括一叠接触电平,每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹入。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。

    THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS
    130.
    发明申请
    THREE DIMENSIONAL MEMORY ARRAY ADJACENT TO TRENCH SIDEWALLS 有权
    三维尺寸记忆阵列

    公开(公告)号:US20130153846A1

    公开(公告)日:2013-06-20

    申请号:US13330525

    申请日:2011-12-19

    IPC分类号: H01L45/00 H01L21/8239

    摘要: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

    摘要翻译: 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠,使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内,使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。