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121.发明申请公开(公告)号：US20180137906A1
公开(公告)日：2018-05-17
申请号：US15855152
申请日：2017-12-27
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Duane R. Mills
CPC classification number: G11C11/2273 , G11C7/1051 , G11C7/1072 , G11C11/2275 , G11C11/2293
Abstract: Methods, systems, and devices for operating a an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM) cell is read onto a first sensing node of a sense amplifier. The reading is performed through a digit line coupling the FeRAM cell to the first sensing node, while the sense amplifier is in an inactive state. A second sensing node of the sense amplifier is biased to a reference voltage provided by a reference voltage source. The biasing is performed while reading the logic value stored in the FeRAM cell onto the first sensing node. The digit line is isolated from the first sensing node after the reading. The sense amplifier is activated, after isolating the digit line from the first sensing node, to amplify and sense a voltage difference between the first sensing node and the second sensing node.
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公开(公告)号：US09886991B1
公开(公告)日：2018-02-06
申请号：US15282029
申请日：2016-09-30
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Duane R. Mills
CPC classification number: G11C11/2273 , G11C7/1051 , G11C7/1072 , G11C11/2275 , G11C11/2293
Abstract: Methods, systems, and devices for operating an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM) cell is read onto a first sensing node of a sense amplifier. The reading is performed through a digit line coupling the FeRAM cell to the first sensing node, while the sense amplifier is in an inactive state. A second sensing node of the sense amplifier is biased to a reference voltage provided by a reference voltage source. The biasing is performed while reading the logic value stored in the FeRAM cell onto the first sensing node. The digit line is isolated from the first sensing node after the reading. The sense amplifier is activated, after isolating the digit line from the first sensing node, to amplify and sense a voltage difference between the first sensing node and the second sensing node.
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公开(公告)号：US09858978B2
公开(公告)日：2018-01-02
申请号：US15377767
申请日：2016-12-13
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati
CPC classification number: G11C11/221 , G11C7/062 , G11C11/2273 , G11C11/2275
Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
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公开(公告)号：US20170358328A1
公开(公告)日：2017-12-14
申请号：US15688667
申请日：2017-08-28
Applicant: Micron Technology, Inc.
Inventor： Gerald John Barkley , Daniele Vimercati , Pierguido Garofalo
CPC classification number: G11C5/025 , G11C7/1042 , G11C8/12 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
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公开(公告)号：US09767898B2
公开(公告)日：2017-09-19
申请号：US15210391
申请日：2016-07-14
Applicant: Micron Technology, Inc.
Inventor： Efrem Bolandrina , Daniele Vimercati
CPC classification number: G11C13/0033 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/79
Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.
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Patent Agency Ranking
公开(公告)号：US20170047117A1
公开(公告)日：2017-02-16
申请号：US15210391
申请日：2016-07-14
Applicant: Micron Technology, Inc.
Inventor： Efrem Bolandrina , Daniele Vimercati
IPC: G11C13/00
CPC classification number: G11C13/0033 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2213/79
Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.
Abstract translation: 在一个实施例中，公开了诸如存储器件的装置。 该装置包括存储单元，数字线驱动器，存取线驱动器，钳位元件和控制电路。 存储单元和钳位元件都可以耦合到数字线。 控制电路可以被配置为使得钳位元件在一段时间内钳位数字线的电压，同时使数字线驱动器以足以使得能够选择存储器单元的电压电平将数字线偏置。 此外，当数字线的电压处于足够使得能够选择存储器单元的电压电平时，控制电路可被配置为使得存取线驱动器偏置耦合到存储单元的存取线。
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公开(公告)号：US09552864B1
公开(公告)日：2017-01-24
申请号：US15067838
申请日：2016-03-11
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati
CPC classification number: G11C11/221 , G11C7/062 , G11C11/2273 , G11C11/2275
Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g., transistors) connected to digit lines may be compensated by using various operating techniques or additional circuit components, or both. For example, a switching component connected to a digit line may also be connected to an offset capacitor selected to compensate for a threshold voltage offset. The offset capacitor may be discharged in conjunction with a read operation, resulting in a threshold voltage applied to the switching component. This may enable all or substantially all of the stored charge of the ferroelectric memory cell to be extracted and transferred to a sense capacitor through the transistor. A sense amplifier may compare the voltage of the sense capacitor to a reference voltage in order to determine the stored logic state of the memory cell.
Abstract translation: 描述了用于操作铁电存储器单元或单元的方法，系统和装置。 可以通过使用各种操作技术或附加电路部件或两者来补偿连接到数字线的开关部件（例如，晶体管）的阈值电压中的偏移。 例如，连接到数字线的开关元件也可以连接到被选择来补偿阈值电压偏移的偏移电容器。 偏移电容器可以与读取操作一起放电，导致施加到开关部件的阈值电压。 这可以使铁电存储单元的所有或基本上所有存储的电荷被提取并通过晶体管传送到感测电容器。 读出放大器可以将感测电容器的电压与参考电压进行比较，以便确定存储器单元的存储的逻辑状态。
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128.发明申请公开(公告)号：US20160254049A1
公开(公告)日：2016-09-01
申请号：US15152449
申请日：2016-05-11
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Riccardo Muzzetto
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/062 , G11C7/12 , G11C7/14 , G11C8/08 , G11C13/00 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C29/025 , G11C29/028 , G11C2013/0052 , G11C2013/0054 , G11C2029/0409 , G11C2029/1202 , G11C2029/1204 , G11C2207/063 , G11C2213/79
Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.
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公开(公告)号：US09406384B2
公开(公告)日：2016-08-02
申请号：US13687706
申请日：2012-11-28
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Andrea Marmiroli
Abstract: Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between semiconductor circuits may be performed with a test current generator and test current measurement circuit, and adjusting a threshold voltage of a semiconductor component of at least one circuit until the difference between the circuits is at a desired difference may be performed with a program circuit.
Abstract translation: 显示和描述用于改善半导体电路之间的匹配的装置，电路和方法。 可以利用测试电流发生器和测试电流测量电路来测量半导体电路之间的匹配差异，并且可以执行至少一个电路的半导体部件的阈值电压，直到电路之间的差异处于期望的差异为止 与程序电路。
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130.发明授权公开(公告)号：US09406353B2
公开(公告)日：2016-08-02
申请号：US14333164
申请日：2014-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Daniele Vimercati
CPC classification number: G11C7/062 , G11C7/08 , G11C7/12 , H03F3/45762 , H03F2200/261 , H03F2203/45536 , H03F2203/45544 , H03F2203/45551
Abstract: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.
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