公开(公告)号：US11843044B2

公开(公告)日：2023-12-12

申请号：US17578687

申请日：2022-01-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

公开(公告)号：US20230395590A1

公开(公告)日：2023-12-07

申请号：US17805697

申请日：2022-06-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR.

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

公开(公告)号：US20230393339A1

公开(公告)日：2023-12-07

申请号：US17834375

申请日：2022-06-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej Jan Pawlak ,  Michal Rakowski ,  Yusheng Bian

IPC: G02B6/293 ,  G02B6/42

CPC classification number: G02B6/2934 ,  G02B6/4215

Abstract: Structures including stacked photonics chips and methods of fabricating a structure including stacked photonics chips. The structure comprises a first chip including a first waveguide core, a ring resonator adjacent to a portion of the first waveguide core, and a first dielectric layer over the first waveguide core and the ring resonator. The first dielectric layer has a first surface. The structure further comprises a second chip including a second waveguide core and a second dielectric layer over the second waveguide core. The second dielectric layer has a second surface adjacent to the first surface of the first dielectric layer, and the second waveguide core is positioned adjacent to the ring resonator.

公开(公告)号：US11839166B2

公开(公告)日：2023-12-05

申请号：US16840471

申请日：2020-04-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu Cai ,  Shyue Seng Tan ,  Eng Huat Toh

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/841 ,  H10B63/84 ,  H10N70/023 ,  H10N70/063

Abstract: A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.

公开(公告)号：US11837851B2

公开(公告)日：2023-12-05

申请号：US17931933

申请日：2022-09-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur ,  Michal Rakowski ,  Kenneth J. Giewont ,  Karen A. Nummy

IPC: H01S5/00 ,  H01S5/20 ,  H01S5/30 ,  H01S5/223 ,  H01S5/026 ,  H01S5/323 ,  H01S5/02

CPC classification number: H01S5/2018 ,  H01S5/20 ,  H01S5/2231 ,  H01S5/2232 ,  H01S5/3013 ,  H01S5/021 ,  H01S5/026 ,  H01S5/3054 ,  H01S5/32333

Abstract: A laser structure, including: a dielectric matrix formed of a first material; a laser source formed within the dielectric matrix and formed of a semiconductor material; and a plurality of side confining features formed within the dielectric matrix and extending parallel to and along a length of the laser source. The plurality of side confining features are formed of the semiconductor material.

公开(公告)号：US11837653B2

公开(公告)日：2023-12-05

申请号：US17555561

申请日：2021-12-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alvin J. Joseph ,  Andreas Knorr ,  Judson R. Holt

IPC: H01L29/73 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/737 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

公开(公告)号：US11835764B2

公开(公告)日：2023-12-05

申请号：US17588440

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Judson Holt

IPC: G02B6/136 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B2006/12061

Abstract: Waveguide structures and methods of fabricating a waveguide structure. The structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material.

公开(公告)号：US20230387333A1

公开(公告)日：2023-11-30

申请号：US17664741

申请日：2022-05-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L31/0216 ,  H01L31/18 ,  H01L31/105

CPC classification number: H01L31/0216 ,  H01L31/1804 ,  H01L31/105 ,  H01L31/022408

Abstract: A photodetector structure includes a first semiconductor material layer on a first portion of a doped well in a substrate. The photodetector structure includes a second semiconductor layer over the first semiconductor layer. The first and second semiconductor material layers may include an undoped semiconductor material. The photodetector structure includes an insulative collar laterally surrounding the first and second semiconductor material layers. The insulative collar may include a varying horizontal thickness. The photodetector structure includes a doped semiconductor material having an opposite doping polarity relative to the doped well, and positioned over the second semiconductor material layer and the insulating collar.

公开(公告)号：US20230387223A1

公开(公告)日：2023-11-30

申请号：US18366711

申请日：2023-08-08

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： BONG WOONG MUN ,  JEOUNG MO KOO

IPC: H01L29/40

CPC classification number: H01L29/407 ,  H01L29/404

Abstract: The present disclosure generally relates to semiconductor structures for capacitive isolation, and structures incorporating the same. More particularly, the present disclosure relates to capacitive isolation structures for high voltage applications. The present disclosure also relates to methods of forming structures for capacitive isolation and the structures incorporating the same. The disclosed semiconductor structures may enable a smaller device footprint and reduced dimensions of components on an IC chip, whilst ensuring galvanic isolation between circuits.

公开(公告)号：US11828983B2

公开(公告)日：2023-11-28

申请号：US17577162

申请日：2022-01-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ian Melville ,  Nicholas Polomoff ,  Thomas Houghton ,  Koushik Ramachandran ,  Pallabi Das

IPC: G02B6/12 ,  G02B6/10 ,  G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B2006/12061

Abstract: Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.