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    RESET CIRCUITRY PROVIDING INDEPENDENT RESET SIGNAL FOR TRACE AND DEBUG LOGIC
    132.
    发明公开
    RESET CIRCUITRY PROVIDING INDEPENDENT RESET SIGNAL FOR TRACE AND DEBUG LOGIC 审中-公开

    公开(公告)号：US20240241811A1

    公开(公告)日：2024-07-18

    申请号：US18155204

    申请日：2023-01-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Avneep Kumar GOYAL ,  Amritanshu ANAND ,  Satinder Singh MALHI

    IPC: G06F11/36 ,  G06F11/07 ,  G06F11/14

    CPC classification number: G06F11/3656 ,  G06F11/0772 ,  G06F11/1441

    Abstract: In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.

    Static random access memory supporting a single clock cycle read-modify-write operation
    133.
    发明授权
    Static random access memory supporting a single clock cycle read-modify-write operation 有权

    公开(公告)号：US12040013B2

    公开(公告)日：2024-07-16

    申请号：US17861384

    申请日：2022-07-11

    Applicant: STMicroelectronics International N.V.

    Inventor： Praveen Kumar Verma ,  Harsh Rawat

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/418

    Abstract: A memory array includes memory cells forming a data word location accessed in response to a word line signal. A data sensing circuit configured to sense data on bit lines associated with the memory cells. The sensed data corresponds to a current data word stored at the data word location. A data latching circuit latches the sensed data for the current data word from the data sensing circuit. A data modification circuit then performs a mathematical modify operation on the current data word to generate a modified data word. The modified data word is then applied by a data writing circuit to the bit lines for writing back to the memory cells of the memory array at the data word location. The operations are advantageously performed within a single clock cycle.

    ELECTRONIC CIRCUIT WITH MOS TRANSISTORS AND MANUFACTURING METHOD
    135.
    发明公开
    ELECTRONIC CIRCUIT WITH MOS TRANSISTORS AND MANUFACTURING METHOD 审中-公开

    公开(公告)号：US20240213101A1

    公开(公告)日：2024-06-27

    申请号：US18535882

    申请日：2023-12-11

    Applicant: STMicroelectronics International N.V.

    Inventor： Brice ARRAZAT ,  Christian RIVERO

    IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

    CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L27/092

    Abstract: An electronic circuit includes a plurality of transistors including: at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area of a semiconductor substrate and at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area of the semiconductor substrate. Each first active area is delimited by a first insulating region which is recessed with respect to a first surface of the semiconductor substrate by a first depth. Each second active area is delimited by a second insulating region which is flush with the first surface of the semiconductor substrate, or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth.

    TRANSDUCER ASSEMBLY WITH BURIED CAVITIES AND METHOD OF MANUFACTURING THE SAME
    136.
    发明公开
    TRANSDUCER ASSEMBLY WITH BURIED CAVITIES AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240205611A1

    公开(公告)日：2024-06-20

    申请号：US18066148

    申请日：2022-12-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Domenico GIUSTI ,  Fabio QUAGLIA ,  Marco FERRERA ,  Carlo Luigi PRELINI

    IPC: H04R17/00

    CPC classification number: H04R17/00

    Abstract: The present disclosure is directed to transducer assemblies or device in which one or more buried cavities are present within a substrate and define or form one or more membranes along a surface of the substrate. One or more piezoelectric actuators are formed on the one or more membranes and the one or more piezoelectric actuators drive the membranes at an operating frequency with an operating bandwidth of the transducer assemblies. Each of the one or more membranes is anchored at respective portions to a main body portion of the substrate to provide robust and strong anchoring of each of the one or more membranes to push unwanted flexure modes outside the operating bandwidth of the transducer assemblies.

    INTEGRATED CIRCUIT COMPRISING A DIGITAL-TO-ANALOG CONVERTER
    137.
    发明公开
    INTEGRATED CIRCUIT COMPRISING A DIGITAL-TO-ANALOG CONVERTER 审中-公开

    公开(公告)号：US20240204686A1

    公开(公告)日：2024-06-20

    申请号：US18526547

    申请日：2023-12-01

    Applicant: STMicroelectronics International N.V.

    Inventor： Vincent BINET

    IPC: H02M7/53846 ,  H02M7/538 ,  H02M7/5388

    CPC classification number: H02M7/538466 ,  H02M7/53803 ,  H02M7/5388

    Abstract: According to one aspect, an integrated circuit is provided comprising: a digital-to-analog converter (MDAC) configured to convert a digital word (DIGW) into an analog signal (SDAC), a switching circuit including: a first transistor (PMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a second transistor (PMOS2) and a third transistor (NMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a fourth transistor (NMOS2); a voltage control circuit configured to apply a voltage on the source of the first transistor (PMOS1) and on the source of the third transistor (NMOS1) so as to limit a drain-source voltage of the first transistor (PMOS1) and a drain-source voltage of the third transistor (NMOS1) regardless of the value of said digital word.

    Capacitive scan method without display flicker
    139.
    发明授权
    Capacitive scan method without display flicker 有权

    公开(公告)号：US12008200B1

    公开(公告)日：2024-06-11

    申请号：US18169000

    申请日：2023-02-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Kien Beng Tan

    IPC: G06F3/041 ,  G06F3/044

    CPC classification number: G06F3/04184 ,  G06F3/0446

    Abstract: A method for operating a touch sensing panel includes a touchscreen controller determining a first plurality of excitation signals in accordance with a first plurality of codes, wherein a sum of the first plurality of codes is a sequence of numbers having a same absolute value and signs alternating between adjacent numbers in the sequence of numbers. The method further includes the touchscreen controller transmitting each of the first plurality of excitation signals to a respective transmitting (TX) touch sensor of the touch sensing panel simultaneously during a first time frame. The method further includes the touchscreen controller determining touch strengths in accordance with a first plurality of output signals received by a plurality of receiving (RX) touch sensors of the touch sensing panel during the first time frame.

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