公开(公告)号：US10418484B1

公开(公告)日：2019-09-17

申请号：US15920748

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8232 ,  H01L27/112 ,  H01L27/24 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/786

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

公开(公告)号：US10388731B2

公开(公告)日：2019-08-20

申请号：US15925051

申请日：2018-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238

Abstract: A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US10374064B2

公开(公告)日：2019-08-06

申请号：US15901447

申请日：2018-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/225 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US10366931B2

公开(公告)日：2019-07-30

申请号：US16133850

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8238 ,  H01L27/092

Abstract: This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

公开(公告)号：US20190214473A1

公开(公告)日：2019-07-11

申请号：US15867036

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Julien Frougier

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/42392 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

公开(公告)号：US20190214469A1

公开(公告)日：2019-07-11

申请号：US15866855

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48

CPC classification number: H01L29/41733 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/481 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0665

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

公开(公告)号：US10332745B2

公开(公告)日：2019-06-25

申请号：US15597277

申请日：2017-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Ruilong Xie ,  Wenhui Wang ,  Yulu Chen ,  Erik Verduijn ,  Zhengqing John Qi ,  Guoxiang Ning ,  Daniel J. Dechene

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3065

Abstract: Methods of forming printed patterns and structures formed using printed patterns. A first line and a second line are lithographically printed in a first layer composed of photoimageable material with a space arranged between the first line and the second line. A dummy assist feature is also lithographically printed in the photoimageable material of the first layer. A second layer underlying the first layer is etched with the first line, the second line, and the dummy assist feature present as an etch mask. The dummy assist feature is arranged on a portion of the space adjacent to the first line and supports the photoimageable material of the first line during etching.

公开(公告)号：US10319627B2

公开(公告)日：2019-06-11

申请号：US15376831

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/66

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10297664B2

公开(公告)日：2019-05-21

申请号：US15486351

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content can be controlled such that voids created by removal of the silicon germanium have uniform dimensions, and the backfilling of such voids with gate dielectric and gate conductor layers proximate to silicon nanosheets or nanowires results in devices having a uniform effective gate length.

公开(公告)号：US20190148240A1

公开(公告)日：2019-05-16

申请号：US16243863

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.