公开(公告)号：US09985089B2

公开(公告)日：2018-05-29

申请号：US15474233

申请日：2017-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Chao Yang

IPC: H01L23/64 ,  H01L49/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L21/28556 ,  H01L21/31053 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/75 ,  H01L28/86

Abstract: Vertical metal-insulator-metal (MIM) capacitors include a metal conductor including a sidewall; a high k dielectric layer on the sidewall of the metal conductor; and a vertically oriented metal layer on the high k dielectric layer. Also disclosed are methods for fabricating the vertical MIM capacitor, wherein a single patterning/mask process can used to fabricate the vertical MIM capacitor structure.

公开(公告)号：US09960078B1

公开(公告)日：2018-05-01

申请号：US15467113

申请日：2017-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Su Chen Fan ,  Huai Huang ,  Koichi Motoyama ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76843 ,  H01L23/53257 ,  H01L23/53266

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

公开(公告)号：US09953950B2

公开(公告)日：2018-04-24

申请号：US15264492

申请日：2016-09-13

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/27848 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/8302 ,  H01L2224/83896 ,  H01L2225/06524 ,  H01L2924/05042

Abstract: A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first semiconductor structure and second semiconductor structure together. The first semiconductor structure comprises a first wafer; a first dielectric layer; a first interconnect structure; and a first oxide layer. The second semiconductor structure comprises a second wafer; a second dielectric layer; a second interconnect structure; and a second oxide layer. The structure further comprises a first nitride layer residing on a top surface of the first oxide layer formed by a nitridation process of the top surface of the first oxide layer; and a second nitride layer residing on a top surface of the second oxide layer formed by the nitridation process of the top surface of the second oxide layer. Further, the silicon-nitride layer comprises the first nitride layer and the second nitride layer.

公开(公告)号：US09953916B2

公开(公告)日：2018-04-24

申请号：US15423923

申请日：2017-02-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: F24S30/452 ,  E04B1/34357 ,  E04B1/346 ,  E04B7/163 ,  F24S20/61 ,  F24S2030/18 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53238 ,  Y02A30/22 ,  Y02B10/20 ,  Y02E10/47

Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

公开(公告)号：US09953869B2

公开(公告)日：2018-04-24

申请号：US15078066

申请日：2016-03-23

Applicant: International Business Machines Corporation

Inventor： Conal E. Murray ,  Chih-Chao Yang

IPC: H01L21/20 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  C23F4/00 ,  C23F1/44

CPC classification number: H01L21/76879 ,  C23F1/44 ,  C23F4/00 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

公开(公告)号：US09953864B2

公开(公告)日：2018-04-24

申请号：US15251403

申请日：2016-08-30

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76825 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.

公开(公告)号：US09941203B2

公开(公告)日：2018-04-10

申请号：US15639262

申请日：2017-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chih-Chao Yang

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5252 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266

Abstract: An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.

公开(公告)号：US20180096887A1

公开(公告)日：2018-04-05

申请号：US15589229

申请日：2017-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann A.M. Mignot ,  Theodorus E. Standaert ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76844 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865

Abstract: Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is deposited onto exposed surfaces of the substrate. The substrate is exposed to a gaseous ion plasma to remove portions of the metal liner that are horizontally oriented and to reduce a height of the metal liner from portions thereof that are vertically oriented. Subsequently, a trench opening is formed in the interlevel dielectric, wherein the trench opening is connected with the via opening, wherein at least a portion of the metal liner remains on sidewall surfaces within the via opening during the forming of the trench opening. A diffusion barrier liner is deposited within the trench opening and the via opening. A conductive material is formed within remaining portions of the trench opening and the via opening to define the interconnect structure.

公开(公告)号：US09929092B2

公开(公告)日：2018-03-27

申请号：US15349168

申请日：2016-11-11

Applicant: International Business Machines Corporation

Inventor： Conal E. Murray ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/02068 ,  H01L21/02071 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76888 ,  H01L21/76889 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Techniques relate to treating metallic interconnects of semiconductors. A metallic interconnect is formed in a layer. A metallic cap is disposed on top of the metallic interconnect. Any metallic residue, formed during the disposing of the metallic cap, is converted into insulating material.

公开(公告)号：US20180082956A1

公开(公告)日：2018-03-22

申请号：US15813522

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Daniel C Edelstein ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53261

Abstract: A method for constructing an advance conductor structure is described. A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features.