公开(公告)号：US10043878B2

公开(公告)日：2018-08-07

申请号：US15830499

申请日：2017-12-04

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/115 ,  H01L29/423 ,  H01L27/088 ,  H01L29/10 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/04

Abstract: Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.

公开(公告)号：US10002794B2

公开(公告)日：2018-06-19

申请号：US15378261

申请日：2016-12-14

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/732 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L21/308 ,  H01L21/283 ,  H01L29/10

CPC classification number: H01L21/823487 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7827

Abstract: Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.

公开(公告)号：US09997619B1

公开(公告)日：2018-06-12

申请号：US15603611

申请日：2017-05-24

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Jeng-Bang Yau

IPC: H01L29/16 ,  H01L29/732 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7322 ,  H01L29/1608 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/6625

Abstract: A BJT includes a pillar formed on a buried oxide layer that is itself formed on a silicon substrate. The pillar has top and bottom surfaces and sidewalls, the bottom surface contacting the buried oxide layer and opposite the top surface. The pillar forms part of a base of the BJT. Si:C layers are formed on a bottom portion of each of the sidewalls of the pillar and leave a top portion of the sidewalls of the pillar exposed. A doped base contact is formed to contact at least part of the exposed sidewalls in the top portion of the pillar. E/C regions are formed abutting the Si:C layers. Contacts are formed to connect to the doped base contact and to the E/C regions. Methods for forming the BJT are also disclosed.

公开(公告)号：US09947778B2

公开(公告)日：2018-04-17

申请号：US15211457

申请日：2016-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Tak H. Ning ,  Alexander Reznicek

IPC: H01L29/735 ,  H01L29/04 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L21/308

CPC classification number: H01L29/735 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3081 ,  H01L21/76251 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/7317 ,  H01L29/737

Abstract: A method of forming a lateral bipolar junction transistor (LBJT) that includes providing a germanium containing layer on a crystalline oxide layer, and patterning the germanium containing layer stopping on the crystalline oxide layer to form a base region. The method may further include forming emitter and collector extension regions on opposing sides of the base region using ion implantation, and epitaxially forming an emitter region and collector region on the crystalline oxide layer into contact with the emitter and collector extension regions. The crystalline oxide layer provides a seed layer for the epitaxial formation of the emitter and collector regions.

公开(公告)号：US09947775B2

公开(公告)日：2018-04-17

申请号：US15432649

申请日：2017-02-14

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8252

CPC classification number: H01L29/6681 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/8252 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7853 ,  H01L2029/7858

Abstract: A lateral epitaxial growth process is employed to facilitate the fabrication of a semiconductor structure including a stack of suspended III-V or germanium semiconductor nanowires that are substantially defect free. The lateral epitaxial growth process is unidirectional due to the use of masks to prevent epitaxial growth in both directions, which would create defects when the growth fronts merge. Stacked sacrificial material nanowires are first formed, then after masking and etching process to reveal a semiconductor seed layer, the sacrificial material nanowires are removed, and III-V compound semiconductor or germanium epitaxy is performed to fill the void previously occupied by the sacrificial material nanowires.

公开(公告)号：US20180096997A1

公开(公告)日：2018-04-05

申请号：US15602740

申请日：2017-05-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Keith E. Fogel ,  Sivananda K. Kanakasabapathy ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1054 ,  H01L29/161

Abstract: A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

公开(公告)号：US09935185B2

公开(公告)日：2018-04-03

申请号：US15584851

申请日：2017-05-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Stephen W. Bedell ,  Pouya Hashemi ,  Bahman Hekmatshoartabari ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/735 ,  H01L21/02 ,  H01L29/08 ,  H01L21/8249 ,  H01L29/66

CPC classification number: H01L21/02507 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/155 ,  H01L29/165 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

公开(公告)号：US20180069013A1

公开(公告)日：2018-03-08

申请号：US15810654

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Michael A. Guillorn ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/11 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/1108 ,  B82Y10/00 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/41741 ,  H01L29/775 ,  H01L29/78642

Abstract: A memory device includes six field effect transistors (FETs) formed with semiconductor nanowires arranged on a substrate in an orientation substantially perpendicular to the substrate. The semiconductor nanowires have bottom contacts, gate contacts separated in a direction perpendicular to the substrate from the bottom contacts, and top contacts separated in a direction perpendicular to the substrate from the gate contacts. The necessary connections are made among the bottom, gate, and top contacts to form the memory device using first, second, and third metallization layers, the first metallization layer being separated in a direction perpendicular to the substrate from the top contacts, the second metallization layer being separated in a direction perpendicular to the substrate from the first metallization layer, and the third metallization layer being separated in a direction perpendicular to the substrate from the second metallization layer. Vias connect the various contacts to the overlying metallization layers as necessary. A method for forming the memory device is also outlined.

公开(公告)号：US20180053847A1

公开(公告)日：2018-02-22

申请号：US15783749

申请日：2017-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/7827 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

公开(公告)号：US20180053835A1

公开(公告)日：2018-02-22

申请号：US15581140

申请日：2017-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L29/7827 ,  H01L21/02546 ,  H01L21/32133 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66977

Abstract: A vertical field effect transistor includes a first source/drain region formed on or in a substrate. A tapered fin is formed a vertical device channel and has a first end portion attached to the first source/drain region. A second source/drain region is formed on a second end portion of the tapered fin. A gate structure surrounds the tapered fin.