公开(公告)号：US20050173759A1

公开(公告)日：2005-08-11

申请号：US11050915

申请日：2005-02-04

申请人： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

发明人： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

摘要： A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

摘要翻译： 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。

公开(公告)号：US20050167754A1

公开(公告)日：2005-08-04

申请号：US11046722

申请日：2005-02-01

申请人： Hee-Soo Kang ,  Jae-Man Yoon ,  Dong-Gun Park ,  Sang-Yeon Han ,  Young-Joon Ahn ,  Choong-Ho Lee

发明人： Hee-Soo Kang ,  Jae-Man Yoon ,  Dong-Gun Park ,  Sang-Yeon Han ,  Young-Joon Ahn ,  Choong-Ho Lee

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/7851 ,  H01L29/66818 ,  Y10S257/90

摘要： A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.

摘要翻译： 公开了一种翅片式MOSFET及其制造方法。 鳍型MOSFET中的栅极结构通过未经光刻工艺的镶嵌工艺形成。 用于形成沟道区域的杂质被选择性地注入到与栅极结构相邻的半导体衬底的部分中。

公开(公告)号：US09087723B2

公开(公告)日：2015-07-21

申请号：US13754063

申请日：2013-01-30

申请人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

发明人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

摘要翻译： 提供场效应晶体管及其制造方法。 晶体管可以包括具有有源图案的衬底，有源图案具有顶表面和两个侧壁，靠近顶表面的栅极电极和有源图案的侧壁并与有源图案交叉，栅极间隔件覆盖侧壁 栅极电极，栅电极的底面的栅极电介质图案，位于栅电极一侧的有源图案上的源电极，栅电极另一侧的有源图案上的漏电极，以及硅化物图案 分别在源电极和漏电极的表面上。 栅极电介质图案包括至少一个高k层，并且栅极间隔物的介电常数小于栅极电介质图案的介电常数。

公开(公告)号：US08809932B2

公开(公告)日：2014-08-19

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08546865B2

公开(公告)日：2013-10-01

申请号：US13218715

申请日：2011-08-26

申请人： Jong-Ho Lim ,  Choong-Ho Lee ,  Hye-Jin Cho

发明人： Jong-Ho Lim ,  Choong-Ho Lee ,  Hye-Jin Cho

IPC分类号： H01L29/788 ,  G11C11/34

CPC分类号： H01L27/11551

摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件包括多个堆叠的半导体层和形成在多个半导体层中的每一个上并且串联连接的多个存储单元晶体管。 配置在不同的半导体层上的存储单元晶体管被串联连接以包括在多个半导体层中形成电流路径的一个单元串，串联连接到单元串的一个边缘部分的第一选择晶体管和串联连接到单元串的第二选择晶体管 单元格串的其他边缘部分。

公开(公告)号：US08315102B2

公开(公告)日：2012-11-20

申请号：US13289689

申请日：2011-11-04

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C2211/5641

摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

公开(公告)号：US08217467B2

公开(公告)日：2012-07-10

申请号：US12984860

申请日：2011-01-05

申请人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

发明人： Jong-Sun Sel ,  Jung-Dal Choi ,  Choong-Ho Lee ,  Ju-Hyuck Chung ,  Hee-Soo Kang ,  Dong-uk Choi

IPC分类号： H01L21/70

CPC分类号： H01L23/485 ,  H01L21/76804 ,  H01L21/76816 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, a semiconductor memory device includes a substrate that includes a cell array region and a peripheral circuit region. The semiconductor memory device further includes a device isolation pattern on the substrate. The device isolation pattern defines a first active region and a second active region within the cell array region and a third active region in the peripheral circuit region. The semiconductor memory device further includes a first common source region, a plurality of first source/drain regions, and a first drain region in the first active region. The semiconductor memory device further includes a second common source region, a plurality of second source/drain regions, and a second drain region in the second active region. The semiconductor memory device further includes a third source/drain region in the third active region. The semiconductor memory device further includes a common source line contacting the first and second common source regions.

摘要翻译： 在一些实施例中，半导体存储器件包括包括单元阵列区域和外围电路区域的衬底。 半导体存储器件还包括在衬底上的器件隔离图案。 器件隔离图案限定了单元阵列区域内的第一有源区和第二有源区以及外围电路区中的第三有源区。 半导体存储器件还包括第一有源区中的第一公共源极区，多个第一源极/漏极区和第一漏极区。 半导体存储器件还包括第二公共源极区域，多个第二源极/漏极区域和第二有源区域中的第二漏极区域。 半导体存储器件还包括第三有源区中的第三源/漏区。 半导体存储器件还包括与第一和第二公共源极区域接触的公共源极线。

公开(公告)号：US08059469B2

公开(公告)日：2011-11-15

申请号：US12481916

申请日：2009-06-10

申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jeong-Dong Choe ,  Tae-Yong Kim ,  Woo-Jung Kim ,  Dong-Hoon Jang ,  Young-Bae Yoon ,  Ki-Hyun Kim ,  Min-Tai Yu

IPC分类号： G11C11/34

CPC分类号： H01L27/11573 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11568 ,  H01L29/78

摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

摘要翻译： 半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。 驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。 公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

公开(公告)号：US08053347B2

公开(公告)日：2011-11-08

申请号：US12379190

申请日：2009-02-13

申请人： Hee-Soo Kang ,  Byung-Kyu Cho ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Byung-Kyu Cho ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： H01L21/3205

CPC分类号： H01L21/28052 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成多个栅极结构，所述栅极结构各自包括堆叠在栅极导电图案上的硬掩模图案，在栅极结构之间形成至少部分地暴露顶部的绝缘层图案 形成通过选择性地去除硬掩模图案而暴露出栅极导电图案的至少顶表面的沟槽，以及在暴露的栅极导电图案上形成硅化物层的沟槽。

公开(公告)号：US20110170356A1

公开(公告)日：2011-07-14

申请号：US13072022

申请日：2011-03-25

申请人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

发明人： Hee-Soo Kang ,  Choong-Ho Lee ,  Dong-Uk Choi

IPC分类号： G11C16/26

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/11524

摘要： Methods of programming data in a non-volatile memory cell are provided. A memory cell according to some embodiments may include a gate structure that includes a tunnel oxide layer pattern, a floating gate, a dielectric layer and a control gate sequentially stacked on a substrate, impurity regions that are formed in the substrate at both sides of the gate structure, and a conductive layer pattern that is arranged spaced apart from and facing the floating gate. Embodiments of such methods may include applying a programming voltage to the control gate, grounding the impurity regions and applying a fringe voltage to the conductive layer pattern to generate a fringe field in the floating gate.

摘要翻译： 提供了在非易失性存储单元中编程数据的方法。 根据一些实施例的存储器单元可以包括栅极结构，其包括隧道氧化物层图案，浮动栅极，电介质层和顺序堆叠在衬底上的控制栅极，杂质区域形成在衬底的两侧的衬底中 栅极结构以及与浮动栅极间隔开并面对浮栅的导电层图案。 这种方法的实施例可以包括将编程电压施加到控制栅极，使杂质区域接地并且向导电层图案施加边缘电压以在浮动栅极中产生边缘场。