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    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME
    132.
    发明申请
    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME 审中-公开

    公开(公告)号：US20180040370A1

    公开(公告)日：2018-02-08

    申请号：US15231518

    申请日：2016-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C11/56 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

    Memory Arrays and Methods of Forming Memory Arrays
    135.
    发明申请
    Memory Arrays and Methods of Forming Memory Arrays 有权

    公开(公告)号：US20170250341A1

    公开(公告)日：2017-08-31

    申请号：US15596397

    申请日：2017-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666

    Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

    Methods of forming memory arrays
    137.
    发明授权
    Methods of forming memory arrays 有权

    公开(公告)号：US09673393B2

    公开(公告)日：2017-06-06

    申请号：US15145654

    申请日：2016-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666

    Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

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