公开(公告)号：US06946373B2

公开(公告)日：2005-09-20

申请号：US10300189

申请日：2002-11-20

申请人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： C30B25/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/337 ,  H01L21/84 ,  H01L21/477

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US06888221B1

公开(公告)日：2005-05-03

申请号：US10709114

申请日：2004-04-14

申请人： Alvin J. Joseph ,  Qizhi Liu ,  Devendra K. Sadana

发明人： Alvin J. Joseph ,  Qizhi Liu ,  Devendra K. Sadana

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082

CPC分类号： H01L29/66287 ,  H01L21/76243 ,  H01L29/1004 ,  H01L29/732

摘要： A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.

摘要翻译： 一种用于双极晶体管的方法和结构，包括形成在半导体衬底的上表面下方的图案化隔离区域和形成在隔离区域的上表面上的单晶非本征基极。 单晶非本征基底包括位于隔离区的上表面和半导体衬底的上表面之间的半导体衬底的一部分。 双极晶体管还包括单晶本征基，其中单晶外基的一部分与单晶本征基的一部分合并。 隔离区将外部基极与收集器电隔离。 内在和外在的基极将集电极与发射极分开。 外在碱包括外延生长的硅。 隔离区域包括包含氧化物的绝缘体，并且隔离区域包括浅沟槽隔离区域和深沟槽隔离区域中的任何一个。

公开(公告)号：US06875982B2

公开(公告)日：2005-04-05

申请号：US10604989

申请日：2003-08-29

申请人： Stephen W. Bedell ,  John Bruley ,  Anthony G. Domenicucci ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  John Bruley ,  Anthony G. Domenicucci ,  Devendra K. Sadana

IPC分类号： G01N1/28 ,  G01N23/04 ,  H01J37/26

CPC分类号： G01N23/04 ,  G01N2001/2893 ,  H01J37/261 ,  H01J2237/2826

摘要： A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.

摘要翻译： 一种用于在单个基板上制造一系列晶体对的方法和校准标准，使得对之间的d间距差会产生正确间隔的莫尔条纹，以便通过各种放大设置最佳地校准电子显微镜的放大倍率设置 在5000x到200,000x的范围内。 通过在单个基板上制造一系列图案，本发明可以通过在单个基板上制造一系列图案来将莫尔条纹间距定制到所需的放大倍率设置，从而可以使用特定的SGOI结构轻松校准每个放大倍数设置，该SGOI结构通过顶部的简单xy平移 SGOI结构的平面表面，其中不需要将校准样品移入和移出电子显微镜。 该方法和校准标准可用于校准电子显微镜，例如扫描透射电子显微镜和透射电子显微镜。

公开(公告)号：US06825102B1

公开(公告)日：2004-11-30

申请号：US10664714

申请日：2003-09-18

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Shreesh Narasimha ,  Devendra K. Sadana

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Shreesh Narasimha ,  Devendra K. Sadana

IPC分类号： H01L21263

CPC分类号： H01L21/02667 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/2022 ,  Y10S438/933

摘要： A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.

摘要翻译： 提供一种方法，其中对缺陷半导体晶体材料进行非晶化步骤之后进行热处理步骤。 非晶化步骤使部分地或完全地形成缺陷半导体晶体材料的区域，包括表面区域。 接下来进行热处理步骤，以便使缺陷半导体晶体材料的非晶化区域再结晶。 通过从缺陷半导体晶体材料的非非晶化区域的固相晶体再生长，在本发明中实现了重结晶。

公开(公告)号：US06657261B2

公开(公告)日：2003-12-02

申请号：US09757317

申请日：2001-01-09

申请人： Fariborz Assaderaghi ,  Tze-chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Fariborz Assaderaghi ,  Tze-chiang Chen ,  K. Paul Muller ,  Edward J. Nowak ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L29/78603

摘要： A ground-plane SOI device including at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region as well as a method of fabricating the same are provided.

公开(公告)号：US06642090B1

公开(公告)日：2003-11-04

申请号：US10063994

申请日：2002-06-03

申请人： David M. Fried ,  Edward J. Nowak ,  Beth A Rainey ,  Devendra K. Sadana

发明人： David M. Fried ,  Edward J. Nowak ,  Beth A Rainey ,  Devendra K. Sadana

IPC分类号： H01L218238

CPC分类号： H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

摘要： The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

摘要翻译： 因此，本发明提供了克服现有技术的许多缺点的用于形成鳍状场效应晶体管（FET）的器件结构和方法。 具体地，器件结构和方法提供了从批量半导体晶片形成finFET器件的能力，同时提供改进的晶片到晶片器件的均匀性。 具体地说，该方法有助于从散装半导体晶片形成finFET器件，从而改进翅片高度控制。 此外，该方法提供了从散装半导体形成finFET的能力，同时提供散热片之间的隔离以及各个finFET的源极和漏极区域之间的隔离。 最后，该方法还可以提供翅片宽度的优化。 因此，本发明的器件结构和方法提供均匀的finFET制造的优点，同时使用成本效应的体晶片。

公开(公告)号：US06566177B1

公开(公告)日：2003-05-20

申请号：US09427257

申请日：1999-10-25

申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

IPC分类号： H01L2100

CPC分类号： H01L27/10864 ,  H01L27/1087

摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate. The trench capacitor is formed in the substrate and the access transistor is formed on a sidewall of the SOI layer. A polysilicon strap connected to the polysilicon plate of the storage capacitor provides a self-aligned contact to the source of the access transistor. Initially, the buried oxide layer is formed in the wafer. Deep trenches are etched, initially just through the SOI layer and the BOX layer. Protective sidewalls are formed in the trenches. Then, the deep trenches are etched into the substrate. The volume in the substrate is expanded to form a bottle shaped trench. A polysilicon capacitor plate is formed in the deep trenches and conductive polysilicon straps are formed in the trenches between the capacitor plates and the SOI sidewalls. Device regions are defined in the wafer and a sidewall gate is formed in the deep trenches. Shallow trenches isolation (STI) is used to isolate and define cells. Bitlines and wordlines are formed on the wafer.

摘要翻译： 一种绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元及阵列及其制造方法。 存储单元包括通过自对准埋入带连接到垂直存取晶体管的沟槽存储电容器。 掩埋氧化层将SOI层与硅衬底隔离。 沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 连接到存储电容器的多晶硅板的多晶硅带提供与存取晶体管的源极的自对准接触。 最初，在晶圆中形成掩埋氧化物层。 深沟槽被蚀刻，最初刚刚通过SOI层和BOX层。 在沟槽中形成保护侧壁。 然后，将深沟槽蚀刻到衬底中。 衬底中的体积被扩大以形成瓶形沟槽。 在深沟槽中形成多晶硅电容器板，并且在电容器板和SOI侧壁之间的沟槽中形成导电多晶硅带。 在晶片中限定器件区域，并且在深沟槽中形成侧壁栅极。 浅沟槽隔离（STI）用于隔离和定义细胞。 在晶片上形成位线和字线。

公开(公告)号：US06426252B1

公开(公告)日：2002-07-30

申请号：US09427256

申请日：1999-10-25

申请人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

发明人： Carl J. Radens ,  Gary B. Bronner ,  Tze-chiang Chen ,  Bijan Davari ,  Jack A. Mandelman ,  Dan Moy ,  Devendra K. Sadana ,  Ghavam Ghavami Shahidi ,  Scott R. Stiffler

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

摘要： A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon substrate. Deep trenches are etched through the upper surface SOI layer, the BOX layer and into the substrate. Each trench capacitor is formed in the substrate and, the access transistor is formed on a sidewall of the SOI layer. Recesses are formed in the BOX layer at the SOI layer. A polysilicon strap recessed in the BOX layer connects each polysilicon storage capacitor plate to a self-aligned contact at the source of the access transistor. Dopant is implanted into the wafer to define device regions. Access transistor gates are formed along the SOI layer sidewalls. Shallow trenches are formed and filled with insulating material to isolate cells from adjacent cells. Wordlines and bitlines are formed to complete the memory array.

摘要翻译： 绝缘体上硅（SOI）动态随机存取存储器（DRAM）单元，阵列和制造方法。 存储单元包括在分层晶片中的沟槽存储电容器上方的垂直存取晶体管。 形成在硅晶片中的掩埋氧化物（BOX）层将SOI层与硅衬底隔离。 深沟槽通过上表面SOI层，BOX层蚀刻并进入衬底。 每个沟槽电容器形成在衬底中，并且存取晶体管形成在SOI层的侧壁上。 在SOI层的BOX层中形成凹部。 凹陷在BOX层中的多晶硅带将每个多晶硅存储电容器板连接到存取晶体管的源极处的自对准接触。 将掺杂剂注入到晶片中以限定器件区域。 存取晶体管栅极沿SOI层侧壁形成。 形成浅沟槽并填充绝缘材料以将细胞与相邻细胞分离。 形成字词和位线以完成内存数组。

公开(公告)号：US06404014B1

公开(公告)日：2002-06-11

申请号：US09708337

申请日：2000-11-08

申请人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

发明人： Effendi Leobandung ,  Devendra K. Sadana ,  Dominic J. Schepis ,  Ghavam Shahidi

IPC分类号： H01L2701

CPC分类号： H01L21/76264 ,  H01L21/762 ,  H01L21/76278

摘要： A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

摘要翻译： 一种平面绝缘体上硅（SOI）结构及其制造方法。 SOI结构具有硅晶片，氧化物层和硅层。 形成从结构的顶表面延伸到硅晶片并且填充有半导体的沟槽。 沟槽有顶部，底部和侧壁。 侧壁具有侧壁硅部分。 沟槽侧壁的侧壁硅部分被沟槽侧壁氧化物层覆盖。 保护侧壁从沟槽顶部到沟槽底部在沟槽侧壁和沟槽侧壁氧化物层上延伸。

公开(公告)号：US06255145B1

公开(公告)日：2001-07-03

申请号：US09227696

申请日：1999-01-08

申请人： Atul Ajmera ,  Devendra K. Sadana ,  Dominic J. Schepis

发明人： Atul Ajmera ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/26533 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/76267 ,  H01L21/76283

摘要： A process for forming a planar silicon-on-insulator (SOI) substrate comprising a patterned SOI region and a bulk region, wherein the substrate is free of transitional defects. The process comprises removing the transitional defects by creating a self-aligned trench adjacent the SOI region between the SOI region and the bulk region.

摘要翻译： 一种用于形成包括图案化SOI区域和体区域的平面绝缘体上硅（SOI）衬底的工艺，其中所述衬底没有过渡缺陷。 该过程包括通过在SOI区域和体区域之间产生邻近SOI区域的自对准沟槽来去除过渡缺陷。